Circuits for controlling display apparatus

ABSTRACT

The invention relates to methods and apparatus for forming images on a display utilizing a control matrix to control the movement of MEMs-based light modulators.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.11/607,715, filed Dec. 1, 2006 which claims the benefit of U.S.Provisional Patent Application No. 60/811,232, filed Jun. 5, 2006, andalso is a continuation-in-part of U.S. patent application Ser. Nos.11/326,696, 11/326,962, 11/326,900, and 11/326,784, all filed Jan. 6,2006, and which claim the benefit of U.S. Provisional Patent ApplicationNo. 60/676,053, filed Apr. 29, 2005, and U.S. Provisional PatentApplication No. 60/655,827, filed Feb. 23, 2005, and also is acontinuation-in-part of U.S. patent application Ser. No. 11/251,035,filed Oct. 14, 2005, which is a continuation-in-part of U.S. patentapplication Ser. No. 11/218,690, filed Sep. 2, 2005, which claims thebenefit of U.S. Provisional Patent Application No. 60/676,053, filedApr. 29, 2005, and U.S. Provisional Patent Application No. 60/655,827,filed Feb. 23, 2005. Each of the above-identified applications is hereinincorporated by reference in their entirety.

FIELD OF THE INVENTION

In general, the invention relates to the field of imaging displays, inparticular, the invention relates to circuits for controlling lightmodulators incorporated into imaging displays.

BACKGROUND OF THE INVENTION

Displays built from mechanical light modulators are an attractivealternative to displays based on liquid crystal technology. Mechanicallight modulators are fast enough to display video content with goodviewing angles and with a wide range of color and grey scale. Mechanicallight modulators have been successful in projection displayapplications. Direct-view displays using mechanical light modulatorshave not yet demonstrated sufficiently attractive combinations ofbrightness and low power. There is a need in the art for fast, bright,low-powered mechanically actuated direct-view displays. Specificallythere is a need for direct-view displays that can be driven at highspeeds and at low voltages for improved image quality and reduced powerconsumption.

SUMMARY OF THE INVENTION

Such direct-view displays can be manufactured using a array ofMEMS-based light modulators. In one aspect, the invention relates to adirect-view display that includes an array of pixels formed on atransparent substrate and a control matrix for controlling the array ofpixels. Each of pixels in the array of pixels includes a MEMS-basedlight modulator with first and second opposing actuators for controllingthe state of the light-modulator. Suitable MEMS-based light modulatorsinclude shutter-based light modulators and light-tap based modulators.The control matrix includes a number of features for each pixel. Foreach pixel, the control matrix includes a write-enabling switch forenabling the pixel to respond to a data voltage and a data switch forselectively controlling actuation of one or both of the opposingactuators in the pixel. In addition, for each pixel, the control matrixincludes one and only one data voltage interconnect for setting adesired state of the light modulator to form an image by controlling thedata switch. In one embodiment, the same data voltage interconnect isshared among a number of pixels in a column of the array.

In one embodiment, for each pixel, the control matrix also includes avoltage inverter circuit. The voltage inverter circuit, in variousimplementations, is a p-mos inverter circuit, an n-mos inverter circuit,and a CMOS inverter circuit. The voltage inverter circuit, in someinstances is a level shifting inverter. In other instances, the voltageinverter circuit is a transition sharpening inverter or a switchinginverter. In another embodiment, the control matrix includes across-coupled inverter for each pixel. The cross-coupled inverter, inone embodiment electrically couples the first and second actuators toone another. In another embodiment, the cross-coupled inverter comprisesa level shifting inverter.

In various embodiments, each pixel includes a flip flop circuit. In oneembodiment, the flip flop electrically connects the first and secondactuators of the pixel to one another. In another embodiment, the flipflop stores light modulator control instructions. Light modulatorinstructions, in some embodiments may also be stored by a cross-coupledinverter included in the control matrix for each pixel.

In one embodiment in which the light modulators are shutter-based, thefirst and second actuators force the shutters of the light modulatorsrelative to an aperture. The aperture may be formed in a layer ofmaterial on the substrate. In an alternative embodiment, the layer ofmaterial in which the apertures are formed is a transparent substrateother than the substrate on which the light modulators are formed.

In another embodiment, the control matrix includes a global actuationinterconnect that is electrically connected to pixels in at least tworows and at least two columns of the array of pixels. The globalactuation interconnect causes substantially simultaneous actuation ofthe pixels to which it is connected. In one embodiment, the globalactuation interconnect is electrically connected to, and therebycontrols, a discharge transistor included in each pixel of the array.

In still another embodiment, the control matrix includes a first voltageactuation interconnect. The first voltage actuation interconnect isdistinct from the data voltage interconnect and is electricallyconnected to the first actuator. The first actuation voltageinterconnect provides a voltage sufficient to actuate the firstactuator. In another embodiment, the control matrix includes anotherswitch, other than the data switch for regulating the application of thevoltage provided via the first actuation voltage interconnect, for eachpixel in the array. The data switch, in certain embodiments, is atransistor that selectively controls the discharge of the voltageprovided by the first actuation voltage interconnect. Each pixel mayalso have be electrically connected to a common voltage interconnect inthe control matrix that provides a bias voltage to the pixels to whichit is connected.

In a further embodiment, the control matrix includes a second actuationvoltage interconnect. The second actuation voltage interconnect isdistinct from both the data voltage interconnect and the first actuationvoltage interconnect. The second actuation voltage interconnect providesa voltage sufficient to actuate the second actuators of the pixels towhich it is connected. In one embodiment, the application of the voltageprovided by the second actuation voltage interconnect to the secondactuator of a pixel is controlled by the pixel's data switch. In anotherembodiment, the second actuation voltage interconnect directly connectsa display drive to the second actuators of pixels in the array. In someembodiments, the voltage provided by the second actuation voltageinterconnect is insufficient to actuate the second actuator if a voltagegreater than a maintenance voltage is applied to the first actuator.

In another embodiment, the control matrix include an actuation voltageinterconnect that is directly electrically connected to one of theactuators of pixels in multiple rows and in multiple columns of thearray of pixels. The actuation voltage interconnect provides a voltagesufficient to actuate the actuators to which it is connecting barring anopposing voltage being applied to the actuators that oppose theactuators to which the shared actuation voltage interconnect connects.

According to another aspect, the invention relates to a direct-viewdisplay apparatus that includes voltage regulators that substantiallylimits variation in a voltage applied across the actuators in thedisplay that would otherwise be caused by movement of portions of theactuators. In one embodiment, voltage variation is consideredsubstantially limited if, during actuation of an actuator, the voltageacross the actuator varies less than 20% from the voltage needed toinitiate actuation of the actuator. In other embodiments, voltagevariation is considered substantially limited if, during actuation of anactuator, the voltage across the actuator varies less than 10% from thevoltage needed to initiate actuation of the actuator. In still anotherother embodiments, voltage variation is considered substantially limitedif, during actuation of an actuator, the voltage across the actuatorvaries less than 5% from the voltage needed to initiate actuation of theactuator.

The direct-view display apparatus includes an array of pixels formed ona transparent substrate. Each pixel includes a MEMS-based lightmodulator. Suitable MEMS-based light modulators include shutter-basedlight modulators, light-tap based light modulators, andelectrowetting-based light modulators. The MEMS-based light modulatorsinclude at least one electrostatic actuator for changing the state ofthe light modulator.

The direct-view display apparatus also includes a control matrix. Thecontrol matrix is connected to the substrate and includes, for eachpixel, a write-enabling interconnect, a data voltage interconnect, and adata switch. The write-enable interconnect of a pixel enables the pixelto respond to a data voltage applied via the data voltage interconnect.The data switch of a pixel electrically connects to a corresponding datavoltage interconnect. Voltages applied to the pixel's data voltageinterconnect thereby control the state of the pixel's light modulator.

In one embodiment, the voltage regulators are display drivers thatinclude DC voltage sources. The display drivers are connected to lightmodulators in the array by actuation voltage interconnects that aredistinct from the data voltage interconnects. In some embodiments, theactuation voltage interconnect electrically connects directly to pixelactuators. In other embodiments, the actuation voltage interconnectelectrically connects to pixel actuators through a switch, other thanthe data switch, included in the control matrix for each pixel. In oneembodiment, the actuation voltage interconnect provides a substantiallyconstant voltage throughout operation of the display. In otherembodiments, the voltage on the actuation voltage interconnect variesduring operation as a result of variation in display driver output.

In another embodiment, each pixel includes its own voltage regulator. Inone particular embodiment, the voltage regulator is a capacitor inelectrical communication with the electrostatic actuator.

In a third aspect, the invention relates to a direct-view displayapparatus that includes an array of MEMS-based light modulators formedon a transparent substrate. The display apparatus includes a controlmatrix formed on the substrate. The control matrix includes a CMOScircuit for each pixel in the display.

In a fourth aspect, the invention relates to a direct-view displayapparatus that includes a bank-wise addressing feature. The displayapparatus includes a transparent substrate, upon which an array of lightmodulators are formed. Suitable light modulators include, withoutlimitation, shutter-based light modulators, electrowetting-based lightmodulators, and light-tap based light modulators. The array is organizedinto rows and columns. The rows are divided into at least two sets ofrows. Each row in a set of rows is associated with a corresponding rowin another set of rows. The associated rows are collectively referred toas a “group of associated rows.” For each pixel in the array, the lightmodulators include an actuator for controlling the state of the lightmodulator.

The display apparatus also includes a control matrix connected to thesubstrate and the light modulators. For each group of associated rows inthe array, the control matrix includes an electrical connection sharedamong the pixels of the group of associated rows that enables the groupof associated rows to be actuated to an addressed state at substantiallythe same time. These electrical connections allow each group ofassociated rows to be actuated at a different times. In one embodiment,the control matrix includes, for each column in the array, a singlewrite enable switch and a single data store capacitor per set of rows.In another embodiment, the display apparatus includes, for each group ofassociated rows, a second distinct electrical connection shared amongthe pixels of the associated rows. This second electrical connectionprovides an actuation voltage to the light modulators in the pixels toreset the pixels to an initial state. In still another embodiment, thedisplay apparatus includes a charge interconnect that connects to pixelsin multiple rows and in multiple columns. This charge interconnectprovides an actuation voltage to the actuators in the pixels to drivethe light modulators into the addressed state.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing discussion will be understood more readily from thefollowing detailed description of the invention with reference to thefollowing drawings:

FIG. 1A is an isometric view of display apparatus, according to anillustrative embodiment of the invention;

FIG. 1B is a block diagram of the a display apparatus, according to anillustrative embodiment of the invention;

FIG. 2 is an isometric view of a shutter assembly suitable for inclusionin the display apparatus of FIG. 1, according to an illustrativeembodiment of the invention;

FIGS. 3A and 3B are isometric views of a dual-actuated shutter assemblysuitable for inclusion in the display apparatus of FIG. 1, according toan illustrative embodiment of the invention;

FIG. 4A is a top view of an array of shutter assemblies suitable forinclusion in the display apparatus of FIG. 1, according to anillustrative embodiment of the invention;

FIG. 4B is a cross sectional view of an illustrative non-shutter-basedlight modulator suitable for inclusion in various embodiments of theinvention;

FIG. 4C is a cross sectional view of a second illustrativenon-shutter-based light modulator suitable for inclusion in variousembodiments of the invention;

FIG. 5A is a conceptual diagram of a control matrix suitable forcontrolling the shutter assemblies of the display apparatus of FIG. 1,according to an illustrative embodiment of the invention;

FIG. 5B is an isometric view of an array of pixels incorporating thecontrol matrix of FIG. 5A and the shutter assemblies of FIG. 2,according to an illustrative embodiment of the invention;

FIG. 6 is a diagram of a second control matrix suitable for controllingthe shutter assemblies of the display apparatus of FIG. 1 according toan illustrative embodiment of the invention;

FIG. 7 is a diagram of a third control matrix suitable for controllingthe shutter assemblies of the display apparatus of FIG. 1, according toan illustrative embodiment of the invention;

FIG. 8 is a flow chart of a method of addressing the pixels of thecontrol matrix of FIG. 7, according to an illustrative embodiment of theinvention;

FIG. 9 is a diagram of a fourth control matrix suitable for controllingthe shutter assemblies of the display apparatus of FIG. 1, according toan illustrative embodiment of the invention;

FIG. 10 is a flow chart of a method of addressing the pixels of thecontrol matrix of FIG. 9, according to an illustrative embodiment of theinvention;

FIG. 11 is a diagram of a fifth control matrix suitable for controllingthe shutter assemblies of the display apparatus of FIG. 1, according toan illustrative embodiment of the invention;

FIG. 12 is a flow chart of a method of addressing the pixels of thecontrol matrix of FIG. 11, according to an illustrative embodiment ofthe invention;

FIG. 13 is a diagram of a sixth control matrix suitable for controllingthe shutter assemblies of the display apparatus of FIG. 1, according toan illustrative embodiment of the invention;

FIG. 14 is a diagram of a seventh control matrix suitable forcontrolling the shutter assemblies of the display apparatus of FIG. 1,according to an illustrative embodiment of the invention;

FIG. 15 is a diagram of an eighth control matrix suitable forcontrolling the shutter assemblies of the display apparatus of FIG. 1,according to an illustrative embodiment of the invention;

FIG. 16A is a diagram of a ninth control matrix suitable for controllingthe shutter assemblies of the display apparatus of FIG. 1, according toan illustrative embodiment of the invention;

FIG. 16B is a diagram of a tenth control matrix suitable for controllingthe shutter assemblies of the display apparatus of FIG. 1, according toan illustrative embodiment of the invention;

FIG. 16C is a flow chart of a method of addressing the pixels of thecontrol matrix of FIG. 16B, according to an illustrative embodiment ofthe invention;

FIG. 17 is a diagram of an eleventh control matrix suitable forcontrolling the shutter assemblies of the display apparatus of FIG. 1,according to an illustrative embodiment of the invention;

FIG. 18 is a diagram of a twelfth control matrix suitable forcontrolling the shutter assemblies of the display apparatus of FIG. 1,according to an illustrative embodiment of the invention;

FIG. 19 is a diagram of a thirteenth control matrix suitable forcontrolling the shutter assemblies of the display apparatus of FIG. 1,according to an illustrative embodiment of the invention

FIG. 20 is a diagram of a fourteenth control matrix suitable forcontrolling the shutter assemblies of the display apparatus of FIG. 1,according to an illustrative embodiment of the invention;

FIG. 21 is a diagram of a fifteenth control matrix suitable forcontrolling the shutter assemblies of the display apparatus of FIG. 1,according to an illustrative embodiment of the invention;

FIG. 22 is a diagram of a sixteenth control matrix suitable forcontrolling the shutter assemblies of the display apparatus of FIG. 1,according to an illustrative embodiment of the invention;

FIG. 23 is a diagram of a seventeenth control matrix suitable forcontrolling the shutter assemblies of the display apparatus of FIG. 1,according to an illustrative embodiment of the invention;

FIG. 24 is a diagram of an eighteenth control matrix suitable forcontrolling the shutter assemblies of the display apparatus of FIG. 1,according to an illustrative embodiment of the invention;

FIG. 25 is a flow chart of a method of addressing the pixels of thecontrol matrix of FIG. 24, according to an illustrative embodiment ofthe invention;

FIG. 26 is a schematic diagram of yet another suitable control matrixfor inclusion in the display apparatus, according to an illustrativeembodiment of the invention;

FIG. 27 is a schematic diagram of another control matrix suitable forinclusion in the display apparatus, according to an illustrativeembodiment of the invention; and

FIG. 28 includes three charts of voltage variations across portions ofMEMS actuators that may result during actuation, according to variousembodiments of the invention.

DESCRIPTION OF CERTAIN ILLUSTRATIVE EMBODIMENTS

To provide an overall understanding of the invention, certainillustrative embodiments will now be described, including apparatus andmethods for displaying images. However, it will be understood by one ofordinary skill in the art that the systems and methods described hereinmay be adapted and modified as is appropriate for the application beingaddressed and that the systems and methods described herein may beemployed in other suitable applications, and that such other additionsand modifications will not depart from the scope hereof.

FIG. 1A is an isometric view of a display apparatus 100, according to anillustrative embodiment of the invention. The display apparatus 100includes a plurality of light modulators, in particular, a plurality ofshutter assemblies 102 a-102 d (generally “shutter assemblies 102”)arranged in rows and columns. In the display apparatus 100, shutterassemblies 102 a and 102 d are in the open state, allowing light topass. Shutter assemblies 102 b and 102 c are in the closed state,obstructing the passage of light. By selectively setting the states ofthe shutter assemblies 102 a-102 d, the display apparatus 100 can beutilized to form an image 104 for a projection or backlit display, ifilluminated by lamp 105. In another implementation the apparatus 100 mayform an image by reflection of ambient light originating from the frontof the apparatus. Preferably, the display apparatus 100 is a direct-viewdisplay in which light modulated by the shutter assemblies 102 isintroduced through a backlight and is directed to a viewer withoutprojection onto an intervening screen.

In the display apparatus 100, each shutter assembly 102 corresponds to apixel 106 in the image 104. In other implementations, the displayapparatus 100 may utilize a plurality of shutter assemblies to form apixel 106 in the image 104. For example, the display apparatus 100 mayinclude three color-specific shutter assemblies 102. By selectivelyopening one or more of the color-specific shutter assemblies 102corresponding to a particular pixel 106, the display apparatus 100 cangenerate a color pixel 106 in the image 104. In another example, thedisplay apparatus 100 includes two or more shutter assemblies 102 perpixel 106 to provide grayscale in an image 104. With respect to animage, a “pixel” corresponds to the smallest picture element defined bythe resolution of image. With respect to structural components of thedisplay apparatus 100, the term “pixel” refers to the combinedmechanical and electrical components utilized to modulate the light thatforms a single pixel of the image.

Each shutter assembly 102 includes a shutter 108 and an aperture 109. Toilluminate a pixel 106 in the image 104, the shutter 108 is positionedsuch that it allows light to pass through the aperture 109 towards aviewer. To keep a pixel 106 unlit, the shutter 108 is positioned suchthat it obstructs the passage of light through the aperture 109. Theaperture 109 is defined by an opening patterned through a reflective orlight-absorbing material in each shutter assembly 102.

The display apparatus also includes a control matrix connected to thesubstrate and to the shutter assemblies for controlling the movement ofthe shutters. The control matrix includes a series of electricalinterconnects (e.g., interconnects 110, 112, and 114), including atleast one write-enable interconnect 110 (also referred to as a“scan-line interconnect”) per row of pixels, one data interconnect 112for each column of pixels, and one common interconnect 114 providing acommon voltage to all pixels, or at least pixels from both multiplecolumns and multiples rows in the display apparatus 100. In response tothe application of an appropriate voltage (the “write-enabling voltage,V_(we)”), the write-enable interconnect 110 for a given row of pixelsprepares the pixels in the row to accept new shutter movementinstructions. The data interconnects 112 communicate the new movementinstructions in the form of data voltage pulses. The data voltage pulsesapplied to the data interconnects 112, in some implementations, directlycontribute to an electrostatic movement of the shutters. In otherimplementations, the data voltage pulses control switches (also referredto as “data switches”), e.g., transistors or other non-linear circuitelements that control the application of separate actuation voltages,which are typically higher in magnitude than the data voltages, to theshutter assemblies 102. The application of these actuation voltages thenresults in the electrostatic movement of the shutters 108.

FIG. 1B is a block diagram 150 of the display apparatus 100. In additionto the elements of the display apparatus 100 described above, asdepicted in the block diagram 150, the display apparatus 100 includes aplurality of scan drivers 152 (also referred to as “write enablingvoltage sources”) and a plurality of data drivers 154 (also referred toas “data voltage sources”). The scan drivers 152 apply write enablingvoltages to scan-line interconnects 110. The data drivers 154 apply datavoltages to the data interconnects 112. In some embodiments of thedisplay apparatus, the data drivers 154 are configured to provide analogdata voltages to the shutter assemblies, especially where the gray scaleof the image 104 is to be derived in analog fashion. In analog operationthe shutter assemblies 102 are designed such that when a range ofintermediate voltages is applied through the data interconnects 112there results a range of intermediate open states in the shutters 108and therefore a range of intermediate illumination states or gray scalesin the image 104.

In other cases the data drivers 154 are configured to apply only areduced set of 2, 3, or 4 digital voltage levels to the control matrix.These voltage levels are designed to set, in digital fashion, either anopen state or a closed state to each of the shutters 108.

The scan drivers 152 and the data drivers 154 are connected to digitalcontroller circuit 156 (also referred to as the “controller 156”). Thecontroller includes a display interface 158 which processes incomingimage signals into a digital image format appropriate to the spatialaddressing and the gray scale capabilities of the display. The pixellocation and gray scale data of each image is stored in a frame buffer159 so that the data can be fed out as needed to the data drivers 154.The data is sent to the data drivers 154 in mostly serial fashion,organized in predetermined sequences grouped by rows and by imageframes. The data drivers 154 can include series to parallel dataconverters, level shifting, and for some applications digital to analogvoltage converters.

All of the drivers (e.g., scan drivers 152, data drivers 154, actuationdriver 153 and global actuation driver 155) for different displayfunctions are time-synchronized by a timing-control 160 in thecontroller 156. Timing commands coordinate the illumination of red,green and blue lamps 162, 164, and 166 via lamp drivers 168, thewrite-enabling and sequencing of specific rows of the array of pixels,the output of voltages from the data drivers 154, and for the output ofvoltages that provide for shutter actuation.

The controller 156 determines the sequencing or addressing scheme bywhich each of the shutters 108 in the array can be re-set to theillumination levels appropriate to a new image 104. New images can 104be set at periodic intervals. For instance, for video displays, thecolor images 104 or frames of the video are refreshed at frequenciesranging from 10 to 300 Hertz. In some embodiments the setting of animage frame is synchronized with the illumination of a backlight suchthat alternate image frames are illuminated with an alternating seriesof colors, such as red, green, and blue. The image frames for eachrespective color is referred to as a color sub-frame. In this method,referred to as the field sequential color method, if the colorsub-frames are alternated at frequencies in excess of 20 Hz, the humanbrain will average the alternating frame images into the perception ofan image having a broad and continuous range of colors.

If the display apparatus 100 is designed for the digital switching ofshutters 108 between open and closed states, the controller 156 cancontrol the addressing sequence and/or the time intervals between imageframes to produce images 104 with appropriate gray scale. The process ofgenerating varying levels of grayscale by controlling the amount of timea shutter 108 is open in a particular frame is referred to as timedivision gray scale. In one embodiment of time division gray scale, thecontroller 156 determines the time period or the fraction of time withineach frame that a shutter 108 is allowed to remain in the open state,according to the illumination level or gray scale desired of that pixel.In another embodiment of time division gray scale, the frame time issplit into, for instance, 15 equal time-duration sub-frames according tothe illumination levels appropriate to a 4-bit binary gray scale. Thecontroller 156 then sets a distinct image into each of the 15sub-frames. The brighter pixels of the image are left in the open statefor most or all of the 15 sub-frames, and the darker pixels are set inthe open state for only a fraction of the sub-frames. In anotherembodiment of time-division gray scale, the controller circuit 156alters the duration of a series of sub-frames in proportion to thebit-level significance of a coded gray scale word representing anillumination value. That is, the time durations of the sub-frames can bevaried according to the binary series 1, 2, 4, 8 . . . . The shutters108 for each pixel are then set to either the open or closed state in aparticular sub-frame according to the bit value at a correspondingposition within the binary word for its intended gray level.

A number of hybrid techniques are available for forming gray scale whichcombine the time division techniques described above with the use ofeither multiple shutters 108 per pixel or via the independent control ofbacklight intensity. These techniques are described further below.

Addressing the control matrix, i.e., supplying control information tothe array of pixels, is, in one implementation, accomplished by asequential addressing of individual lines, sometimes referred to as thescan lines or rows of the matrix. By applying V_(we) to the write-enableinterconnect 110 for a given scan line and selectively applying datavoltage pulses V_(d) to the data interconnects 112 for each column, thecontrol matrix can control the movement of each shutter 108 in thewrite-enabled row. By repeating these steps for each row of pixels inthe display apparatus 100, the control matrix can complete the set ofmovement instructions to each pixel in the display apparatus 100.

In one alternative implementation, the control matrix applies V_(we) tothe write-enable interconnects 110 of multiple rows of pixelssimultaneously, for example, to take advantage of similarities betweenmovement instructions for pixels in different rows of pixels, therebydecreasing the amount of time needed to provide movement instructions toall pixels in the display apparatus 100. In another alternativeimplementation, the rows are addressed in a non-sequential, e.g., in apseudo-randomized order, in order to minimize visual artifacts that aresometimes produced, especially in conjunction with the use of a codedtime division gray scale.

In alternative embodiments, the array of pixels and the control matricesthat control the pixels incorporated into the array may be arranged inconfigurations other than rectangular rows and columns. For example, thepixels can be arranged in hexagonal arrays or curvilinear rows andcolumns. In general, as used herein, the term scan-line shall refer toany plurality of pixels that share a write-enabling interconnect.

Shutter Assemblies

FIG. 2 is diagram of an illustrative shutter assembly 200 suitable forincorporation into the display apparatus 100 of FIG. 1. The shutterassembly 200 includes a shutter 202 coupled to an actuator 204. Theactuator 204 is formed from two separate compliant electrode beamactuators 205, as described in U.S. patent application Ser. No.11/251,035, filed on Oct. 14, 2005. The shutter 202 couples on one sideto the actuators 205. The actuators 205 move the shutter transverselyover a surface in a plane of motion which is substantially parallel tothe surface. The opposite side of the shutter couples to a spring 207which provides a restoring force opposing the forces exerted by theactuator 204.

Each actuator 205 includes a compliant load beam 206 connecting theshutter 202 to a load anchor 208. The load anchors 208 along with thecompliant load beams 206 serve as mechanical supports, keeping theshutter 202 suspended proximate to the surface. The surface includes oneor more apertures 211 for admitting the passage of light. The loadanchors 208 physically connect the compliant load beams 206 and theshutter 202 to the surface and electrically connect the load beams 206to a bias voltage, in some instances, ground.

Each actuator 204 also includes a compliant drive beam 216 positionedadjacent to each load beam 206. The drive beams 216 couple at one end toa drive beam anchor 218 shared between the drive beams 216. The otherend of each drive beam 216 is free to move. Each drive beam 216 iscurved such that it is closest to the load beam 206 near the free end ofthe drive beam 216 and the anchored end of the load beam 206.

In operation, a display apparatus incorporating the shutter assembly 200applies an electric potential to the drive beams 216 via the drive beamanchor 218. A second electric potential may be applied to the load beams206. The resulting potential difference between the drive beams 216 andthe load beams 206 pulls the free ends of the drive beams 216 towardsthe anchored ends of the load beams 206, and pulls the shutter ends ofthe load beams 206 toward the anchored ends of the drive beams 216,thereby driving the shutter 202 transversely towards the drive anchor218. The compliant members 206 act as springs, such that when thevoltage across the beams 206 and 216 potential is removed, the loadbeams 206 push the shutter 202 back into its initial position, releasingthe stress stored in the load beams 206.

A shutter assembly, such as shutter assembly 200, that incorporates apassive restoring force mechanism is generally referred to herein as anelastic shutter assembly. A number of elastic restoring mechanisms canbe built into or in conjunction with electrostatic actuators, thecompliant beams illustrated in shutter assembly 200 providing just oneexample. Elastic shutter assemblies can be constructed such that in anunactivated, or relaxed state, the shutters are either opened or closed.For illustrative purposes, it is assumed below that the elastic shutterassemblies described herein are constructed to be closed in theirrelaxed state.

As described in U.S. patent application Ser. No. 11/251,035, referred toabove, depending on the curvature of the drive beams 216 and load beams206, the shutter assembly may either be controlled in a analog ordigital fashion. When the beams have a strongly non-linear or divergentcurvature (beams diverging with more than a second order curvature) theapplication of an analog actuation voltage across drive beams 216 andthe load beams 206 results in a predetermined incremental displacementof the shutter 202. Thus, the magnitude of shutter 202 displacement canbe varied by applying different magnitude voltages across the drivebeams 216 and the load beams 206. Shutter assemblies 200 including morecurved beams are therefore used to implement analog gray scaleprocesses.

For shutter assemblies with less curved beams (beams diverging withsecond order curvature or less), the application of a voltage across thedrive beams 216 and the load beams 206 results in shutter displacementif the voltage is greater than a threshold voltage (V_(at)). Applicationof a voltage equaling or exceeding V_(at) results in the maximum shutterdisplacement. That is, if the shutter 202 is closed absent theapplication of a voltage equaling or exceeding the threshold,application of any voltage equaling or exceeding V_(at) fully opens theshutter. Such shutter assemblies are utilized for implementing timedivision and/or digital area division gray scale processes in variousembodiments of the display apparatus 100.

FIGS. 3A and 3B are isometric views of a second shutter assembly 300suitable for use in the display apparatus 100. FIG. 3A is a view of thesecond shutter assembly 300 in an open state. FIG. 3B is a view of thesecond shutter assembly 300 in a closed state. Shutter assembly 300 isdescribed in further detail in U.S. patent application Ser. No.11/251,035, referenced above. In contrast to the shutter assembly 200,shutter assembly 300 includes actuators 302 and 304 on either side of ashutter 306. Each actuator 302 and 304 is independently controlled. Afirst actuator, a shutter-open actuator 302, serves to open the shutter306. A second actuator, the shutter-close actuator 304, serves to closethe shutter 306. Both actuators 302 and 304 are preferably compliantbeam electrode actuators. The actuators 302 and 304 open and close theshutter 306 by driving the shutter 306 substantially in a plane parallelto a surface 307 over which the shutter is suspended. The shutter 306 issuspended over the surface at via anchors 308 attached to the actuators302 and 304. The inclusion of supports attached to both ends of theshutter 306 along its axis of movement reduces out of plane motion ofthe shutter 306 and confines the motion substantially to the desiredplane of motion. The surface 307 includes at least one aperture 309 foradmitting the passage of light through the surface 307.

FIG. 4A is a top view of an array 400 of shutter assemblies 402 suitablefor inclusion in the display apparatus 100. Each shutter assembly 402includes a shutter 404, a load beam 406, and two drive beams 408. Aswith the shutter assemblies 200 and 300 described above, the shutterassemblies 402 modulate light by transversely driving theircorresponding shutters 404 such that the shutters 404 selectivelyinterfere with light passing through apertures in a surface over whichthe shutters 404 are driven.

To drive one of the shutters in one of the shutter assemblies, a voltageis applied across the load beam 406 and one of the drive beams 408. Togenerate the voltage, a first electric potential is applied to theselected drive beam and a second electric potential is applied to theload beam 406 and to the shutter 404. The first and second electricpotentials may be of the same polarity or they may be of oppositepolarities. They also may have the same magnitude or they may havedifferent magnitudes. Either potential may also be set to ground. Inorder for the shutter assembly to actuate (i.e., for the shutter tochange its position) the difference between the first and secondpotentials must equal or exceed an actuation threshold voltage V_(at).

In most embodiments, V_(at) is reached by applying voltages ofsubstantially different magnitudes to the selected drive beam and theload beam. For example, assuming V_(at) is 40V, the display apparatus100 may apply 30V to the drive beam and −10V to the load beam, resultingin a potential difference of 40V. For purposes of controlling powerdissipation, however, it is also important to consider and control theabsolute voltage applied to each electrode with respect to the ground orpackage potential of the display. The power required to apply electricpotentials to an array of actuators is proportional to the capacitanceseen by the voltage source (P=1/2 fCV²), where f is the frequency of thedrive signal, V is the voltage of the source and C is the totalcapacitance seen by the source. The total capacitance has severaladditive components, including the capacitance that exists between theload beam and drive beam, the source-drain capacitance of transistorsalong an interconnect line between the voltage source and the actuator(particularly for those transistors whose gates are closed), thecapacitance between the interconnect line and its surroundings,including neighboring shutter assemblies and/or crossover lines, and thecapacitance between the load or drive beams and their surroundings,including neighboring shutter assemblies or the display package. Sincethe load beam 406 is electrically coupled to the shutter 404, thecapacitance of the load beam 406 includes the capacitance of the shutter404. Since the shutter comprises typically a large fraction of area ofthe pixel, the capacitance between the load beam and its surroundingscan represent a significant fraction of the total capacitance seen bythe voltage source. Furthermore, because of the difference in area ofthe combined load beam 406 and shutter 404 and the area of the drivebeam 408 is significant, the capacitance between the load beam and itssurroundings is typically much larger than that between the drive beamand its surroundings. As a result, the CV² power loss experienced byvoltage sources connected to either the drive or the load beams will besignificantly different even if the range of their voltage excursionswere to be the same. For this reason, it is generally advantageous toconnect the higher capacitance end of the actuator, i.e., the load beam,to a voltage source that either does not change in voltage significantlywith respect to ground or package potential, or to a voltage source thatdoes not change voltage with the highest frequencies required by thedrive system. For example, if a 40 volt difference is required betweenthe load beam 406 and the drive beam 408 to actuate the actuator, itwill be advantageous if the voltage difference between the drive beamand the ground or case potential represents at least half if not most ofthe 40 volts.

The dashed line overlaid on the shutter assembly array 400 depicts thebounds of a single pixel 410. The pixel 410 includes two shutterassemblies 402, each of which may be independently controlled. By havingtwo shutter assemblies 402 per pixel 410, a display apparatusincorporating the shutter assembly array 400 can provide three levels ofgray scale per pixel using area division gray scale. More particularly,the pixel could be driven into the following states: both shutterassemblies closed; one shutter assembly opened and one shutter assemblyclosed; or both shutter assemblies open. Thus, the resulting image pixelcan be off, at half brightness, or at full brightness. By having eachshutter assembly 402 in the pixel 410 have different sized apertures, adisplay apparatus could provide yet another level of gray scale usingonly area division gray scale. The shutter assemblies 200, 300 and 402of FIGS. 2, 3 and 4A can be made bi-stable. That is, the shutters canexist in at least two equilibrium positions (e.g. open or closed) withlittle or no power required to hold them in either position. Moreparticularly, the shutter assembly 300 can be mechanically bi-stable.Once the shutter of the shutter assembly 300 is set in position, noelectrical energy or holding voltage is required to maintain thatposition. The mechanical stresses on the physical elements of theshutter assembly 300 can hold the shutter in place.

The shutter assemblies 200, 300, and 402 can also be made electricallybi-stable. In an electrically bi-stable shutter assembly, there exists arange of voltages below the actuation voltage of the shutter assembly,which if applied to a closed actuator (with the shutter being eitheropen or closed), hold the actuator closed and the shutter in position,even if an opposing force is exerted on the shutter. The opposing forcemay be exerted by a spring attached to an opposite end of the shutter,such as spring 207 in shutter assembly 200, or the opposing force may beexerted by an opposing actuator. The minimum voltage needed to maintaina shutter's position against such an opposing force is referred to as amaintenance voltage V_(m).

Electrical bi-stability arises from the fact that the electrostaticforce across an actuator is a strong function of position as well asvoltage. The beams of the actuators in the shutter assemblies 200, 300,and 402 act as capacitor plates. The force between capacitor plates isproportional to 1/d² where d is the local separation distance betweencapacitor plates. In a closed actuator, the local separation betweenactuator beams is very small. Thus, the application of a small voltagecan result in a relatively strong force between the actuator beams. As aresult, a relatively small voltage, such as V_(m), can keep the actuatorclosed, even if other elements exert an opposing force on the actuator.

In shutter assemblies, such as 300, that provide for two separatelycontrollable actuators (for the purpose of opening and closing theshutter respectively), the equilibrium position of the shutter will bedetermined by the combined effect of the voltage differences across eachof the actuators. In other words, the electrical potentials of all threeterminals (the shutter open drive beam, the shutter close drive beam,and the shutter/load beams), as well as shutter position, must beconsidered to determine the equilibrium forces on the shutter.

For an electrically bi-stable system, a set of logic rules can describethe stable states, and can be used to develop reliable addressing ordigital control schemes for the shutter. These logic rules are asfollows:

Let V_(s) be the electrical potential on the shutter or load beam. LetV_(o) be the electrical potential on the shutter-open drive beam. LetV_(c) be the electrical potential on the shutter-close drive beam. Letthe expression /V_(o)−V_(s)/ refer to the absolute value of the voltagedifference between the shutter and the shutter-open drive beam. LetV_(m) be the maintenance voltage. Let V_(at) be the actuation thresholdvoltage, i.e., the voltage necessary to actuate an actuator absent theapplication of V_(m) to an opposing drive beam. Let V_(max) be themaximum allowable potential for V_(o) and V_(c). LetV_(m)<V_(at)<V_(max). Then, assuming V_(o) and V_(c) remain belowV_(max):

1. If /V_(o)−V_(S)/<V_(m) and /V_(c)−V_(s)/<V_(m)

Then the shutter will relax to the equilibrium position of itsmechanical spring.

2. If /V_(o)−V_(S)/>V_(m) and /V_(c)−V_(s)/>V_(m)

Then the shutter will not move, i.e. it will hold in either the open orthe closed state, whichever position was established by the lastactuation event.

3. If /V_(o)−V_(s)/>V_(at) and /V_(c)−V_(s)/<V_(m)

Then the shutter will move into the open position.

4. If N_(o)−V_(s)/<V_(m) and /V_(c)−V_(s)/>V_(at)

Then the shutter will move into the closed position.

Following rule 1, with voltage differences on each actuator near tozero, the shutter will relax. In many shutter assemblies themechanically relaxed position is only partially open or closed, and sothis voltage condition is preferably avoided in an addressing scheme.

The condition of rule 2 makes it possible to include a global actuationfunction into an addressing scheme. By maintaining a shutter voltagewhich provides beam voltage differences that are at least themaintenance voltage, the absolute values of the shutter open and shutterclosed potentials can be altered or switched in the midst of anaddressing sequence over wide voltage ranges (even where voltagedifferences exceed V_(at)) with no danger of unintentional shuttermotion.

The condition of rules 3 and 4 are those that are generally targetedduring the addressing sequence to ensure the bi-stable actuation of theshutter.

The maintenance voltage difference, V_(m), can be designed or expressedas a certain fraction of the actuation threshold voltage, V_(at). Forsystems designed for a useful degree of bi-stability the maintenancevoltage can exist in a range between 20% and 80% of V_(at). This helpsensure that charge leakage or parasitic voltage fluctuations in thesystem do not result in a deviation of a set holding voltage out of itsmaintenance range—a deviation which could result in the unintentionalactuation of a shutter. In some systems an exceptional degree ofbi-stability or hysteresis can be provided, with V_(m) existing over arange of 2% to 98% of V_(at). In these systems, however, care must betaken to ensure that an electrode voltage condition of V<V_(m) can bereliably obtained within the addressing and actuation time available.

Alternative MEMS-Based Light Modulators

The control matrices described herein are not limited to controllingshutter-based MEMS light modulators, such as the light modulatorsdescribed above. For example, FIG. 4B is a cross sectional view of alight tap-based light modulator 450, suitable for inclusion in variousones of the control matrices described below. As described further inU.S. Pat. No. 5,771,321, entitled “Micromechanical Optical Switch andFlat Panel Display,” the entirety of which is incorporated herein byreference, a light tap works according to a principle of frustratedtotal internal reflection. That is, light 452 is introduced into a lightguide 454, in which, without interference, light 452 is for the mostpart unable to escape the light guide 454 through its front or rearsurfaces due to total internal reflection. The light tap 450 includes atap element 456 that has a sufficiently high index of refraction that,in response to the tap element 456 contacting the light guide 454, light452 impinging on the surface of the light guide adjacent the tap element456 escapes the light guide 454 through the tap element 458 towards aviewer, thereby contributing to the formation of an image.

In one embodiment, the tap element 456 is formed as part of beam 458 offlexible, transparent material. Electrodes 460 coat portions one side ofthe beam 458. Opposing electrodes 460 are disposed on a cover plate 464positioned adjacent the layer 458 on the opposite side of the lightguide 454. By applying a voltage across the electrodes 460, the positionof the tap element 456 relative to the light guide 454 can be controlledto selectively extract light 452 from the light guide 454.

The light tap 450 is only one example of a non-shutter-based MEMSmodulator suitable for control by the control matrices described herein.Other forms of non-shutter-based MEMS modulators could likewise becontrolled by various ones of the control matrices described hereinwithout departing from the scope of the invention.

FIG. 4C is a cross sectional view of a second illustrativenon-shutter-based light modulator suitable for inclusion in variousembodiments of the invention Specifically, FIG. 4C is a cross sectionalview of an electrowetting-based light modulation array 470. The lightmodulation array 470 includes a plurality of electrowetting-based lightmodulation cells 472 a-472 d (generally “cells 472”) formed on anoptical cavity 474. The light modulation array 470 also includes a setof color filters 476 corresponding to the cells 472.

Each cell 472 includes a layer of water (or other transparent conductiveor polar fluid) 478, a layer of light absorbing oil 480, a transparentelectrode 482 (made, for example, from indium-tin oxide) and aninsulating layer 484 positioned between the layer of light absorbing oil480 and the transparent electrode 482. Illustrative implementation ofsuch cells are described further in U.S. Patent Application PublicationNo. 2005/0104804, published May 19, 2005 and entitled “Display Device.”In the embodiment described herein, the electrode takes up a portion ofa rear surface of a cell 472.

The remainder of the rear surface of a cell 472 is formed from areflective aperture layer 486 that forms the front surface of theoptical cavity 474. The reflective aperture layer 486 is formed from areflective material, such as a reflective metal or a stack of thin filmsforming a dielectric mirror. For each cell 472, an aperture is formed inthe reflective aperture layer 486 to allow light to pass through. Theelectrode 482 for the cell is deposited in the aperture and over thematerial forming the reflective aperture layer 486, separated by anotherdielectric layer.

The remainder of the optical cavity 474 includes a light guide 488positioned proximate the reflective aperture layer 486, and a secondreflective layer 490 on a side of the light guide 488 opposite thereflective aperture layer 486. A series of light redirectors 491 areformed on the rear surface of the light guide, proximate the secondreflective layer. The light redirectors 491 may be either diffuse orspecular reflectors. One of more light sources 492 inject light 494 intothe light guide 488.

In an alternative implementation, an additional transparent substrate ispositioned between the light guide 490 and the light modulation array470. In this implementation, the reflective aperture layer 486 is formedon the additional transparent substrate instead of on the surface of thelight guide 490.

In operation, application of a voltage to the electrode 482 of a cell(for example, cell 472 b or 472 c) causes the light absorbing oil 480 inthe cell to collect in one portion of the cell 472. As a result, thelight absorbing oil 480 no longer obstructs the passage of light throughthe aperture formed in the reflective aperture layer 486 (see, forexample, cells 472 b and 472 c). Light escaping the backlight at theaperture is then able to escape through the cell and through acorresponding color (for example, red, green, or blue) filter in the setof color filters 476 to form a color pixel in an image. When theelectrode 482 is grounded, the light absorbing oil 480 covers theaperture in the reflective aperture layer 486, absorbing any light 494attempting to pass through it.

The area under which oil 480 collects when a voltage is applied to thecell 472 constitutes wasted space in relation to forming an image. Thisarea cannot pass light through, whether a voltage is applied or not, andtherefore, without the inclusion of the reflective portions ofreflective apertures layer 486, would absorb light that otherwise couldbe used to contribute to the formation of an image. However, with theinclusion of the reflective aperture layer 486, this light, whichotherwise would have been absorbed, is reflected back into the lightguide 490 for future escape through a different aperture.

Control Matrices and Methods of Operation Thereof

FIG. 5A is a conceptual diagram of a control matrix 500 suitable forinclusion in the display apparatus 100 for addressing an array ofpixels. FIG. 5B is an isometric view of a portion of an array of pixelsincluding the control matrix 500. Each pixel 501 includes an elasticshutter assembly 502, such as shutter assembly 200, controlled by anactuator 503.

The control matrix 500 is fabricated as a diffused orthin-film-deposited electrical circuit on the surface of a substrate 504on which the shutter assemblies 502 are formed. The control matrix 500includes a scan-line interconnect 506 for each row of pixels 501 in thecontrol matrix 500 and a data-interconnect 508 for each column of pixels501 in the control matrix 500. Each scan-line interconnect 506electrically connects a write-enabling voltage source 507 to the pixels501 in a corresponding row of pixels 501. Each data interconnect 508electrically connects an data voltage source, (“Vd source”) 509 to thepixels 501 in a corresponding column of pixels. In control matrix 500,the data voltage V_(d) provides the majority of the energy necessary foractuation. Thus, the data voltage source 509 also serves as an actuationvoltage source.

For each pixel 501 or for each shutter assembly in the array, thecontrol matrix 500 includes a transistor 510 and a capacitor 512. Thegate of each transistor is electrically connected to the scan-lineinterconnect 506 of the row in the array in which the pixel 501 islocated. The source of each transistor 510 is electrically connected toits corresponding data interconnect 508. The shutter assembly 502includes an actuator with two electrodes. The two electrodes havesignificantly different capacitances with respect to the surroundings.The transistor connects the data interconnect 508 to the actuatorelectrode having the lower capacitance. More particularly the drain ofeach transistor 510 is electrically connected in parallel to oneelectrode of the corresponding capacitor 512 and to the lowercapacitance electrode of the actuator. The two electrodes of theactuator in the shutter assembly 502 have significantly differentcapacitances. The drain of the transistor 510 electrically connects tothe electrode having the lower capacitance. The other electrode of thecapacitor 512 and the higher capacitance electrode of the actuator inshutter assembly 502 are connected to a common or ground potential. Inalternate implementations, the pixel 501 forgoes a capacitor 512 whichis distinct from the shutter assembly 502 and instead relies on thecapacitance inherent in the shutter assembly 502 in the pixel 501 tostore the voltage needed to achieve and maintain the shutter assembly502 state.

In operation, to form an image, the control matrix 500 write-enableseach row in the array in sequence by applying V_(we) to each scan-lineinterconnect 506 in turn. For a write-enabled row, the application ofV_(we) to the gates of the transistors 510 of the pixels 501 in the rowallows the flow of current through the data interconnects 508 throughthe transistors to apply a potential to the actuator of the shutterassembly 502. While the row is write-enabled, data voltages V_(d) areselectively applied to the data interconnects 508. In implementationsproviding analog gray scale, the data voltage applied to each datainterconnect 508 is varied in relation to the desired brightness of thepixel 501 located at the intersection of the write-enabled scan-lineinterconnect 506 and the data interconnect 508. In implementationsproviding digital control schemes, the data voltage is selected to beeither a relatively low magnitude voltage (i.e., a voltage near ground)or to meet or exceed V_(at) (the actuation threshold voltage). Inresponse to the application of V_(at) to a data interconnect 508, theactuator in the corresponding shutter assembly 502 actuates, opening theshutter in that shutter assembly 502. The voltage applied to the datainterconnect 508 remains stored in the capacitor 512 of the pixel evenafter the control matrix 500 ceases to apply V_(we) to a row. It is notnecessary, therefore, to wait and hold the voltage V_(we) on a row fortimes long enough for the shutter assembly 502 to actuate; suchactuation can proceed after the write-enabling voltage has been removedfrom the row. The voltage in the capacitors 510 in a row remainsubstantially stored until an entire video frame is written, and in someimplementations until new data is written to the row.

The control matrix 500 can be manufactured through use of the followingsequence of processing steps:

First an aperture layer 550 is formed on a substrate 504. If thesubstrate 504 is opaque, such as silicon, then the substrate 504 servesas the aperture layer 550, and aperture holes 554 are formed in thesubstrate 504 by etching an array of holes through the substrate 504. Ifthe substrate 504 is transparent, such as glass, then the aperture layer550 may be formed from the deposition of a light blocking layer on thesubstrate 504 and etching of the light blocking layer into an array ofholes. The aperture holes 554 can be generally circular, elliptical,polygonal, serpentine, or irregular in shape. As described in U.S.patent application Ser. No. 11/218,690, filed on Sep. 2, 2005, if thelight blocking layer is also made of a reflective material, such as ametal, then the aperture layer 550 can act as a mirror surface whichrecycles non-transmitted light back into an attached backlight forincreased optical efficiency. Reflective metal films appropriate forproviding light recycling can be formed by a number of vapor depositiontechniques including sputtering, evaporation, ion plating, laserablation, or chemical vapor deposition. Metals that are effective forthis reflective application include, without limitation, Al, Cr, Au, Ag,Cu, Ni, Ta, Ti, Nd, Nb, Si, Mo and/or alloys thereof. Thicknesses in therange of 30 nm to 1000 nm are sufficient.

Second, an intermetal dielectric layer is deposited in blanket fashionover the top of the aperture layer metal 550.

Third, a first conducting layer is deposited and patterned on thesubstrate. This conductive layer can be patterned into the conductivetraces of the scan-line interconnect 506. Any of the metals listedabove, or conducting oxides such as indium tin oxide, can havesufficiently low resistivity for this application. A portion of the scanline interconnect 506 in each pixel is positioned to so as to form thegate of a transistor 510.

Fourth, another intermetal dielectric layer is deposited in blanketfashion over the top of the first layer of conductive interconnects,including that portion that forms the gate of the transistor 510.Intermetal dielectrics sufficient for this purpose include SiO₂, Si₃N₄,and Al₂O₃ with thicknesses in the range of 30 nm to 1000 nm.

Fifth, a layer of amorphous silicon is deposited on top of theintermetal dielectric and then patterned to form the source, drain andchannel regions of a thin film transistor active layer. Alternativelythis semiconducting material can be polycrystalline silicon.

Sixth, a second conducting layer is deposited and patterned on top ofthe amorphous silicon. This conductive layer can be patterned into theconductive traces of the data interconnect 508. The same metals and/orconducting oxides can be used as listed above. Portions of the secondconducting layer can also be used to form contacts to the source anddrain regions of the transistor 510.

Capacitor structures such as capacitor 512 can be built as plates formedin the first and second conducting layers with the interveningdielectric material.

Seventh, a passivating dielectric is deposited over the top of thesecond conducting layer.

Eighth, a sacrificial mechanical layer is deposited over the top of thepassivation layer. Vias are opened into both the sacrificial layer andthe passivation layer such that subsequent MEMS shutter layers can makeelectrical contact and mechanical attachment to the conducting layersbelow.

Ninth, a MEMS shutter layer is deposited and patterned on top of thesacrificial layer. The MEMS shutter layer is patterned with shutters 502as well as actuators 503 and is anchored to the substrate 504 throughvias that are patterned into the sacrificial layer. The pattern of theshutter 502 is aligned to the pattern of the aperture holes 554 thatwere formed in the first aperture layer 550. The MEMS shutter layer maybe composed of a deposited metal, such as Au, Cr or Ni, or a depositedsemiconductor, such as polycrystalline silicon or amorphous silicon,with thicknesses in the range of 300 nanometers to 10 microns.

Tenth, the sacrificial layer is removed such that components of the MEMSshutter layer become free to move in response to voltages that areapplied across the actuators 503.

Eleventh, the sidewalls of the actuator 503 electrodes are coated with adielectric material to prevent shorting between electrodes with opposingvoltages.

Many variations on the above process are possible. For instance thereflective aperture layer 550 of step 1 can be combined into the firstconducting layer. Gaps are patterned into this conducting layer toprovide for electrically conductive traces within the layer, while mostof the pixel area remains covered with a reflective metal. In anotherembodiment, the transistor 510 source and drain terminals can be placedon the first conducting layer while the gate terminals are formed in thesecond conducting layer. In another embodiment the semiconductingamorphous or polycrystalline silicon is placed directly below each ofthe first and second conducting layers. In this embodiment vias can bepatterned into the intermetal dielectric so that metal contacts can bemade to the underlying semiconducting layer.

In an alternative implementation, the shutter assembly 502, along withthe control matrix 500, can be fabricated on a separate substrate fromthe one on which the aperture layer 550 is formed. In such animplementation, the substrate on which the control matrix 500 andshutter assembly 500 are formed is aligned with the substrate 504 onwhich the aperture layer 550 is formed such that the shutters align withtheir corresponding aperture holes 554.

FIG. 6 is a diagram of a second control matrix 600 suitable forinclusion in the display apparatus 100 for addressing an array of pixels602. The pixels 602 in the control matrix 600 forgo the use of atransistor and capacitor, as are included in control matrix 500, infavor of a metal-insulator-metal (“MIM”) diode 604. The control matrix600 includes a scan-line interconnect 606 for each row of pixels 602 inthe control matrix 600 and a data interconnect 607 for each column ofpixels in the control matrix 600. Each scan-line interconnect 606electrically connects to one terminal of the MIM diode 604 of each pixel602 in its corresponding row of pixels 602. The other terminal of theMIM diode 604 in a pixel 602 electrically connects to one of the twoelectrodes of a shutter assembly 608, such as shutter assembly 200, inthe pixel 602.

In operation the MIM diode 604 acts as a non-linear switch element whichprevents current from flowing to the shutter assembly 609 unless thevoltage presented between the scan line interconnect 606 and the dataline interconnect 607 exceeds a threshold voltage V_(diode). Therefore,if voltage pulses provided by the data line interconnect 607 do notexceed V_(diode), such data pulses will not effect that actuation ofshutter assemblies 608 connected along the data line. If, however, awrite-enabling voltage V_(we), is applied to a scan line interconnect606 such that a voltage difference in excess of V_(diode) appearsbetween the scan line interconnect 606 and any of the several data lineinterconnects 607 that cross the scan line interconnect 606, then theshutters at the intersection of the that scan line interconnect 606 andthose data line interconnects 607 will receive their charge and can beactuated. In implementations providing analog gray scale, the datavoltage applied to each data interconnect 607 is varied in relation tothe desired brightness of the pixel 602 located at the intersection ofthe write-enabled scan-line interconnect 606 and the data interconnect607. In implementations providing a digital control schemes, the datavoltage is selected to be either close to V_(we) (i.e., such that littleor no current flows through the diode 604) or high enough such thatV_(we)-−V_(diode) will meet or exceed V_(at) (the actuation thresholdvoltage).

In other implementations the MIM diode 604 can be placed between theshutter assembly 608 and the data line interconnect 607. The method ofoperation is the same as described above. In other implementations, twoMIM diodes are employed, each connected to a separate and adjacent scanline. One electrode of the shutter assembly is connected to each of theMIM diodes on the side opposite of their respective scan lines such thatthe voltage appearing on the shutter electrode is almost ½ of thevoltage difference between the two scan lines. In this fashion it iseasier to fix the potential of one of the electrodes of the actuator toa known zero or common potential.

The two electrodes of the shutter assembly 608 in the pixel 602 havesignificantly different capacitances with respect to the ground or casepotential. Of these two electrodes, the higher capacitance electrode ispreferably connected to the scan line interconnect 606 (optionally, asshown, with a diode connected between shutter 608 and the scan lineinterconnect 606), since the scan line typically requires smallervoltage changes (with respect to ground) than are typically required ofthe data line interconnect 607. The data interconnect 607 electricallyconnects to the lower-capacitance electrode of the shutter assembly 608.

FIG. 7 is a diagram of a third control matrix 700 for controlling pixels702 incorporating shutter assemblies 703 with both open and closeactuators, such as shutter assemblies 300 and 402. The control matrix700 includes scan-line interconnect 704 per row of pixels 702 in thecontrol matrix 700 and two data interconnects 706 a and 706 b addressingeach column of pixels 702 in the control matrix 700. One of the datainterconnects is a shutter-open interconnect 706 a and the other datainterconnect is a shutter-close interconnect 706 b.

For a given pixel 702 in the control matrix 700, the pixel 702 includestwo transistor-capacitor pairs, one pair for each data-interconnect 706a and 706 b addressing the pixel. The gates of both transistors in thepixel 702 electrically couple to the scan-line interconnect 704corresponding to the row of the control matrix 700 in which the pixel702 is located. The source of one of the transistors, the shutter-opentransistor 708 a, electrically connects to the shutter-opendata-interconnect 706 a of the column in which the pixel 702 is located.The drain of the shutter-open transistor 708 a electrically connects, inparallel, to one electrode of one of the capacitors, the shutter-opencapacitor 710 a, and to one electrode of the shutter-open actuator ofthe shutter assembly 703 of the pixel. The other electrode of theshutter-open capacitor 710 a electrically connects to ground or to abias interconnect set to a common voltage among the pixels 702.

Similarly, the source of the other transistor in the pixel 702, theshutter-close transistor 708 b, electrically connects to theshutter-close data interconnect 706 b of the column in which the pixel702 is located. The drain of the shutter-close transistor 708 belectrically connects, in parallel, to the other of the capacitors inthe pixel, the shutter-close capacitor 710 b, and to one of theelectrodes of the shutter-close actuator of the shutter assembly 703.

Both the shutter-open actuator and the shutter-close actuator of theshutter assembly 703 include two electrodes. One electrode in eachactuator has a significantly higher capacitance than the other. Thedrains of the shutter-open and the shutter-close transistorselectrically connect to the lower-capacitance electrodes of theircorresponding actuators. The ground or bias interconnect, if any,electrically connects to the higher-capacitance electrode.

The control matrix of FIG. 7 employs n-channel transistors. Otherembodiments are possible that employ p-channel MOS transistors. In otherimplementations, the transistors 708 a and 708 b can be replaced by MIMdiodes or other non-linear circuit elements or switches. In otherimplementations the capacitors 710 a and 710 b can be removedaltogether, their function replaced by the effective capacitance of theshutter-open and shutter-closed actuators.

In the case where multiple shutters are to be actuated within eachpixel, a separate pair of shutter-open data interconnects andshutter-closed data interconnects, along with associated transistors andcapacitors, can be provided for each shutter within the pixel.

FIG. 8 is flow chart of a method 800 of addressing the pixels 702controlled by the control matrix 700 of FIG. 7 to form an image frame.The steps carried out to address a single image frame are referred tocollectively as a “frame addressing cycle.” The method begins bywrite-enabling the first scan line in the display (step 802). To do so,the control matrix 700 applies V_(we), (e.g., +45V for nMOS transistorsor −45V for pMOS transistors), to the scan line interconnect 704 in thecontrol matrix 700 corresponding to the first row in the control matrixand grounds the other scan-line interconnects 704.

The control matrix 700 then writes data to each pixel 702 in thewrite-enabled scan line (decision block 804 to step 812). The datacorresponds to the desired states of the shutter assemblies 703 in thosepixels 702. For ease of understanding, the data writing process(decision block 804 to step 812) is described below in relation to asingle pixel 702 in a selected column in the write-enabled scan line. Atthe same time data is written to this single pixel 702, the controlmatrix 700 also writes data in the same fashion to the remaining pixels702 in the write-enabled scan line.

To write data to a pixel 702 at the intersection of a selected column ofthe control matrix 700 and the write-enabled scan line first, atdecision block 804, it is determined if the shutter assembly 703 inquestion is to be open in the next image frame or closed. If the shutterassembly 703 is to be open, the control matrix 700 applies a datavoltage, V_(d), to the shutter-open interconnect 706 a of the selectedcolumn (step 806). V_(d) is selected to raise the voltage across theelectrodes of the shutter-open actuator in the shutter assembly 703 toequal or exceed the voltage necessary for actuation, V_(at). At aboutthe same time that the control matrix 700 applies V_(d) to theshutter-open interconnect 706 a of the selected column (step 806), thecontrol matrix 700 grounds the shutter-close interconnect 706 b of thecolumn (step 808).

If, at decision block 804, it is determined that the shutter assembly703 is to be closed, the control matrix 700 applies the data voltageV_(d) to the shutter-close interconnect 706 b (step 810) and grounds theshutter-open interconnect 706 a of the column (step 812). Once thevoltage across the electrodes of the desired actuator builds up toV_(at), the actuator, if not previously in the desired position,actuates (step 814), moving the shutter in the shutter assembly 703 tothe desired position.

After the data is written to the pixels 702 in the scan line in steps806-812, the control matrix 700 grounds the scan-line interconnect 704(step 814) and write-enables the next scan line (step 816). The processrepeats until all pixels 702 in the control matrix 700 are addressed. Inone implementation, before addressing the first scan line in the controlmatrix 700, a backlight to which the control matrix is affixed is turnedoff. Then, after all scan lines in the control matrix 700 have beenaddressed, the backlight is turned back on. Synchronizing the switchingof the backlight off and on with the beginning and end of a periodduring which a frame is addressed improves the color purity of theresultant image since then the backlight is on only when all pixels arealready set to their correct image state.

An actuation event is determined by noting the voltage differences thatappear across the shutter-open actuator and the shutter closed actuator.For consistent actuation, generally one of these voltage differenceswill be kept close to zero, or at least below a certain maintenancevoltage V_(m), while the absolute value of the other voltage differencewill exceed the actuation voltage. Consistent with the actuationconditions described with respect to FIGS. 2, 3, and 4A, the polaritiesof applied voltages, such as V_(d), can be either negative or positive,and the voltage applied to the common potential (indicated as “ground”in FIG. 7 or at step 812), can be any voltage either positive ornegative.

In some implementations, it is advantageous to periodically oroccasionally reverse the sign of the voltages that appear across theactuators of shutter assembly 703 without otherwise altering the method800 of addressing the pixels. In one case, polarity reversal can beaccomplished by maintaining the common electrode of all shutters 703 ata potential close to zero while reversing the polarity of the datavoltage, V_(d). In another case polarity reversal can be accomplished bysetting the common voltage to V_(common), where V_(common) is equal toor greater than V_(at), and then providing a voltage source such thatthe data voltage either alternates between V_(common) and 2*V_(at) orbetween zero and V_(common).

Similar advantageous use of polarity reversals and the use of non-zerocommon voltages can be applied to the control matrices 500 and 600.

The flow chart of method 800 is drawn for the case where only digitalinformation is written into an image frame, i.e. where the shutters areintended to be either open or closed. A similar method of image frameaddressing can be employed for the provision of gray scale images builtupon loading analog data through data interconnects 706 a and 706 b. Inthis case, intermediate voltages are intended to produce only partialopenings of the shutters 703. The voltages applied across theshutter-open actuators will tend to move the shutters in directionsopposite to the motion induced by voltages across the shutter-closedactuators. There will exist, however, pairs of complementary voltagesthat, when applied simultaneously across these two actuators, willresult in controlled and pre-determined states of partial shutteropening.

The complementary nature of the voltages supplied to either theshutter-open interconnect 706 a or the shutter-closed interconnect 706 bcan be used to advantage if the voltage source electronics are alsodesigned with capability for charge recycling. Taking as an examplemethod 800, which is designed for the loading of digital information tothe image frame: voltages loaded into the interconnects at steps 806 or810 are complementary. That is, if V_(d) is loaded into one of theinterconnects, then the other interconnect is usually grounded. Changingthe state of the shutter assembly 703 (e.g. from closed to open) isconceptually, then, a matter of transferring the charge stored on oneactuator over to its opposing actuator. If the energy lost on each ofthese transitions is Q*V_(d), where Q is the charge stored on anactuator, then considerable power savings can be derived if the storedcharge is not simply dissipated as waste energy in the voltage sourceelectronics at each transition but is instead recycled for use on theother actuator. While complete charge recycling is difficult, methodsfor partial recycling are available. For example, the frame addressingmethod 800 can provide a step where the data line interconnects 706 aand 706 b are shorted together within the voltage source electronics fora brief period between steps 802 and 804. For the brief period in whichthese interconnects are shorted they will share the stored charge, so atleast a fraction of the previous charge becomes available on whicheverof the data line interconnects is to be brought back into its fullycharged state.

FIG. 9 is another illustrative control matrix 900 suitable foraddressing an array of pixels in display device 100. The control matrix900 is similar to the control matrix 700. That is, the control matrix900 includes a scan-line interconnect 904 for each row of pixels in thecontrol matrix 900 and two data interconnects, a shutter-openinterconnect 906 a and a shutter-close interconnect 906 b, for eachcolumn of pixels 902 in the control matrix. In addition, each pixel inthe control matrix 900 includes a shutter open-transistor (or optionallya diode or varistor) 908 a, a shutter-close transistor (or optionally adiode or varistor) 908 b, a shutter-open capacitor 910 a, ashutter-close actuator 910 b, and a shutter assembly 912. The shutterassembly is either mechanically and/or electrically bi-stable. Thecontrol matrix 900, however, includes an additional controllableinterconnect, a global actuation interconnect 914. The global actuationinterconnect 914 substantially simultaneously provides about the samevoltage (a “common voltage”) to pixels 902 in at least two rows and twocolumns of the control matrix 900. In one implementation, the globalactuation interconnect 914 provides a common voltage to all pixels 902in the control matrix 900. The higher capacitance electrode of theactuators of the shutter assemblies 912 in each pixel 902 in the controlmatrix 900 electrically connect to the global actuation interconnect 914instead of to ground.

The inclusion of the global actuation interconnect 914 enables the nearsimultaneous actuation of pixels 902 in multiple rows of the controlmatrix 900. As a result, all actuators that actuate to set a given imageframe (e.g., all shutters that move) can be actuated at the same time,as opposed to a row by row actuation method as described in method 800.The use of a global actuation process temporally decouples the writingof data to a pixel 902 from the actuation the shutter assembly 912 inthe pixel 902.

The global actuation feature incorporated into the control matrix 900takes advantage of the bi-stability of the shutter assemblies 912 in thecontrol matrix 900. Actuating an electrically bi-stable shutter assemblyrequires that two conditions be satisfied simultaneously, that theabsolute value of voltage across one electrode exceeds V_(at), while theabsolute value of the voltage across the other electrode is less than amaintenance voltage V_(m). Thus, for control matrix 900, when a voltagein excess of V_(m) is applied to one actuator of a shutter assembly 912,applying V_(at) to the opposing shutter assembly is insufficient tocause the actuator to actuate.

For example, assume that the shutter-open actuator of an electricallybi-stable shutter assembly has a V_(at) of 40V. At the same time, theapplication of 10V maintenance voltage across the electrodes of theshutter-close actuator may keep the shutter of the shutter assembly in aclosed position even when 60V is applied across the electrodes of theshutter-open actuator. If a −10V bias potential is applied between thehigher-capacitance electrodes of all shutter assemblies and ground viathe global common interconnect, while the ground potential is applied toone of the actuation electrodes, then a data voltage of +40V can beapplied to the lower-capacitance electrodes of selected actuators in theshutter assemblies, thereby yielding a +50V potential difference acrossthose actuators, without causing the actuators to actuate. Then, bygrounding the global common interconnect, the voltage across theelectrodes of the selected actuators is reduced to +40V while thevoltage across the opposing actuator is removed. As +40V still equalsthe actuation voltage of the actuator and no maintenance voltage iskeeping the opposing actuator in position, the selected actuators allmove in concert. Another example is described in further detail below inrelation to FIG. 10.

FIG. 10 is flow chart of a method 1000 of addressing an image frameusing the control matrix 900 of FIG. 9. The method begins by setting theglobal common interconnect 914 to a maintenance voltage V_(m), e.g., ½V_(at) (step 1001) with respect to ground. Then, the control matrix 900write-enables the first scan line in the display (step 1002). To do so,the control matrix 900 applies V_(we), e.g., +45V, to a first scan-lineinterconnect 904 in the control matrix 900 and grounds the otherscan-line interconnects 904.

The control matrix 900 then writes data to each pixel 902 in thewrite-enabled scan line corresponding to the desired states of thosepixels in the next image frame (decision block 1004 to step 1012). Thedata writing process is described below in relation to a single pixel902 in a selected column in the write-enabled scan line. At the sametime that data is written to this single pixel 902, the control matrix900 also writes data in the same fashion to the remaining pixels 902 inthe write-enabled scan line.

To write data to a pixel 902, at decision block 1004, it is determinedif the shutter of the shutter assembly 912 in the pixel 902 is to be inthe open position in the next image frame or in the closed position. Ifthe shutter is to be in the open position, the control matrix 900applies a data voltage, V_(d), to the shutter-open interconnect of theselected column (step 1006). V_(d) is selected such that before theapplication of a global actuation voltage, V_(ag), to the global commoninterconnect 914, the voltage across the shutter-open actuator in thepixel 902 remains insufficient to overcome the bias applied to theshutter-close actuator, but such that after the application of V_(ag) tothe global common interconnect 914, the voltage across the electrodes ofthe shutter-open actuator is sufficient for the shutter-open actuator toactuate. For example, if V_(at) equals 40V, V_(m) equals 20V, and V_(ag)equals ground, then V_(d) is selected to be greater than or equal to40V, but less than the potential that would overcome V_(m). At the sametime that the control matrix 900 applies V_(d) to the shutter-openinterconnect 906 a of the selected column (step 1006), the controlmatrix 900 grounds the shutter-close interconnect 906 b of the column(step 1008).

If at decision block 1004, it is determined that the shutter is to be inthe off position, the control matrix 900 applies the data voltage V_(d)to the shutter-close interconnect 906 b (step 1010) and grounds theshutter-open interconnect 906 a of the column (step 1012).

After the control matrix 900 writes data to the pixels 902 in thewrite-enabled scan line in steps 1006-1012, the control matrix 900grounds the currently write-enabled scan-line interconnect 904 (step1014) and write-enables the next scan line (step 1016). The processrepeats until all pixels 902 in the control matrix 900 are addressed(see decision block 1015). After all pixels in the control matrix 900are addressed (see decision block 1015), the control matrix 900 appliesthe global common voltage V_(ag) to the global common interconnect (step1018), thereby resulting in a near simultaneous global actuation of theshutter assemblies 912 in the control matrix 900. Thus, for suchimplementations, the global common interconnect serves as a globalactuation interconnect.

As with the method 800, the method 1000 may also include thesynchronization of a backlight with shutter actuation. However, by usingthe global actuation process described above, the backlight can be kepton for a larger percentage of the time a display is in operation,therefore yielding a brighter display for the same level of drivingpower in a backlight. In one embodiment, a backlight is synchronizedsuch that it is off when ever the shutters in one row of a controlmatrix are set for one image frame while shutters in other rows of thecontrol matrix are set for a different image frame. In control matricesthat do not employ global actuation, for every frame of video, thebacklight is turned off during the entire data writing process(approximately 500 microseconds to 5 milliseconds), as each row ofpixels actuates as it is addressed. In contrast, in control matricesusing global actuation, the backlight can remain on while the datawriting process takes place because no pixels change state until afterall the data has been written. The backlight is only turned off (if atall), during the much shorter time beginning after the last scan line iswritten to, and ending a sufficient time after the global actuationvoltage is applied for the pixels to have changed states (approximately10 microseconds to 500 microseconds).

An actuation event in the method 1000 is determined by noting thevoltage differences that appear across the shutter-open actuator and theshutter closed actuator. Consistent with the actuation conditionsdescribed with respect to FIGS. 2, 3, and 4A, the polarities of appliedvoltages, such as V_(d), can be either negative or positive, and thevoltage applied to the global common interconnect can be any voltageeither positive or negative.

In other implementations it is possible to apply the method 1000 of FIG.10 to a selected portion of a whole array of pixels, since it may beadvantageous to update different areas or groupings of rows and columnsin series. In this case a number of different global actuationinterconnects 914 could be routed to selected portions of the array forselectively updating and actuating different portions of the array.

In some implementations it is advantageous to periodically oroccasionally reverse the sign of the voltages that appear across theactuators of shutter assembly 912 without otherwise altering the method1000 of addressing the pixels. In one such case polarity reversal can beaccomplished by reversing the signs of most of the potentials employedin Method 1000, with the exception of the write-enable voltage. Inanother cases voltages similar to those used in Method 1000 can beapplied but with a complementary logic. Table 1 shows the differencesbetween the nominal voltage assignments as described above for method1000 and the voltages which could be applied in order to achievepolarity reversal on the electrodes of the shutter assemblies. In thefirst case, called Polarity Reversal Method 1, the voltages which appearacross actuator electrodes are merely reversed in sign. Instead ofapplying V_(d) to the shutter-open electrode, for instance, −V_(d) wouldbe applied. For the case where nMOS transistors are employed for thetransistors 908 a and 908 b, however, a voltage shift should be employed(both gate voltages shifting down by an amount V_(d)). These gatevoltage shifts ensure that the nMOS transistors operate correctly withthe new voltages on the data interconnects.

TABLE 1 Polarity Polarity Action: Reversal Reveral “Close the Shutter”Method 1000 Method 1 Method 2 Non-Enabled Row Voltage ground −V_(d)ground Write-Enable Voltage V_(we) −V_(d) + V_(we) V_(we) Voltage onshutter-closed V_(d) −V_(d) ground interconnect Voltage on shutter-openground ground V_(d) interconnect Maintenance Voltage V_(m) −V_(m) V_(m)Global Actuation Voltage V_(ag) −V_(ag) V_(d) (near ground) (nearground)

Table 1 also shows a second method, Polarity Reversal Method 2, whichallows the use of similar voltages (without having to reverse signs onany interconnect drivers), but still achieves polarity reversal acrossall actuators. This is accomplished by driving the global actuationinterconnect to the higher voltage, V_(d), instead of toward ground asin Method 1000 in order to move selected shutters. The sequence ofvoltage changes in Polarity Reversal Method 2 is similar to that ofMethod 1000, except that a complementary logic is now employed at step1004 when assigning voltages to the actuators of each pixel. In thisMethod 2, if the shutter is to be closed, then the shutter-openinterconnect would be brought up to the potential V_(d), while theshutter-closed interconnect would be grounded. In this example, afterthe global actuation interconnect is brought from its maintenancepotential V_(m) up to the actuation potential V_(d), the potentialacross the shutter-open actuator would be near to zero (certainly lessthan V_(m)), while the potential across the shutter-closed actuatorwould be −V_(d), sufficient to actuate the shutter to the closedposition and with a polarity that is the reverse of what was applied inMethod 1000. Similarly if, at step 1004, the shutter is to be openedthen the shutter-closed interconnect would be brought up to thepotential Vd while the shutter-open interconnect is grounded.

The control matrix 900 can alternate between the voltages used in Method1000 and that used with the above Polarity Reversal Methods in everyframe or on some other periodic basis. Over time, the net potentialsapplied across the actuators on shutter assemblies 1408 by the chargeinterconnect 1406 and the global actuation interconnect 1416 average outto about 0V.

Actuation methods, similar to method 1000, can also be applied tosingle-sided or elastic shutter assemblies, such as with shutterassemblies 502 in control matrix 500. Such single-sided applicationswill be illustrated in conjunction with FIG. 14 below.

FIG. 11 is a diagram of another control matrix 1100 suitable forinclusion in the display apparatus 100. As with control matrices 700 and900, the control matrix 1100 includes a series of scan-lineinterconnects 1104, with one scan-line interconnect 1104 correspondingto each row of pixels 1102 in the control matrix 1100. The controlmatrix 1100 includes a single data interconnect 1106 for each column ofpixels 1102 in the control matrix. As such, the control matrix 1100 issuitable for controlling elastic shutter assemblies 1108, such asshutter assembly 200. As with actuator in shutter assembly 200, theactuators in the shutter assemblies 1108 in the control matrix 1100 haveone higher-capacitance electrode and one lower-capacitance electrode.

In addition to the scan-line and data-interconnects 1104 and 1106, thecontrol matrix 1100 includes a charge interconnect 1110 (also labeled asV(at)) and a charge trigger interconnect 1112 (also labeled as C-T). Thecharge interconnect 11100 and the charge trigger interconnect 1112 maybe shared among all pixels 1102 in the control matrix 1100, or somesubset thereof. For example, each column of pixels 1100 may share acommon charge interconnect 1110 and a common charge trigger interconnect1112. The following description assumes the incorporation of a globallyshared charge interconnect 1110 and a globally common charge triggerinterconnect 1112.

Each pixel 1102 in the control matrix 1100 includes two transistors, acharge trigger switch transistor 1114 and a discharge switch transistor1116. The gate of the charge trigger switch transistor 1114 iselectrically connected to the charge trigger interconnect 1112 of thecontrol matrix 1100. The drain of the charge trigger switch transistor1114 is electrically connected to the charge interconnect 1110. Thecharge interconnect 1110 receives a DC voltage sufficient to actuate theactuators of the shutter assembly 1108 in each pixel 1102, absent theapplication of any bias voltage to the scan line interconnect 1104. Thesource of the charge trigger switch transistor 1114 is electricallyconnected to the lower capacitance electrode of the actuator in theshutter assembly 1108 in the pixel 1102 and to the drain of thedischarge switch transistor 1116. The gate of the discharge switchtransistor 1116 is electrically connected to the data interconnect 1106of the column of the control matrix 1100 in which the pixel 1102 islocated. The source of the discharge switch transistor 1116 iselectrically connected to the scan-line interconnect 1104 of the row ofthe control matrix 1100 in which the pixel 1102 is located. Thehigher-capacitance electrode of the actuator in the shutter assembly1108 is also electrically connected to the scan-line interconnect 1104of row corresponding to the pixel. Alternately, the higher capacitanceelectrode can be connected to a separate ground or common electrode.

FIG. 12 is a flow chart of a method 1200 of addressing the pixelsincorporated into a control matrix, such as control matrix 1100,according to an illustrative embodiment of the invention. At thebeginning of a frame addressing cycle, control matrix 1100 actuates allunactuated actuators of the shutter assemblies 1108 incorporated intothe control matrix 1100, such that all shutter assemblies 1108 are setto the same position (open or closed) (steps 1202-1204). To do so, thecontrol matrix 1100 applies a charge trigger voltage, e.g., 45V, to thecharge trigger interconnect 1112, activating the charge trigger switchtransistors 1114 of the pixels (step 1202). The electrodes of theactuators incorporated into the shutter assemblies 1108 of the pixels1108 serve as capacitors for storing the voltage V_(at) supplied overthe charge interconnect 1110, e.g., 40V. The control matrix 1100continues to apply the charge trigger voltage (step 1202) for a periodof time sufficient for all actuators to actuate, and then the controlmatrix 1100 grounds the charge trigger switch transistor 1114 (step1204). The control matrix 1100 applies a bias voltage V_(b), e.g., 10Vwith respect to ground, to all scan-line interconnects 1104 in thecontrol matrix 1100 (step 1206).

The control matrix 1100 then proceeds with the addressing of each pixel1102 in the control matrix, one row at a time (steps 1208-1212). Toaddress a particular row, the control matrix 1100 write-enables a firstscan line by grounding the corresponding scan-line interconnect 1104(step 1208). Then, at decision block 1210, the control matrix 1100determines for each pixel 1102 in the write-enabled row whether thepixel 1102 needs to be switched out of its initial frame position. Forexample, if at step 1202, all shutters are opened, then at decisionblock 1210, it is determined whether each pixel 1102 in thewrite-enabled row is to be closed. If a pixel 1102 is to be closed, thecontrol matrix 1100 applies a data voltage, for example 5V, to the datainterconnect 1106 corresponding to the column in which that pixel 1102is located (step 1212). As the scan-line interconnect 1104 for thewrite-enabled row is grounded (step 1208), the application of the datavoltage V_(d) to the data interconnect 1106 of the column results in apotential difference between the gate and the source of the dischargeswitch transistor 1116 of the correct sign and magnitude to open thechannel of the transistor 1116. Once the channel of transistor 1116 isopened the charge stored in the shutter assembly actuator can bedischarged to ground through the scan line interconnect 1104. As thevoltage stored in the actuator of the shutter assembly 1108 dissipates,the restoring force or spring in the shutter assembly 1108 forces theshutter into its relaxed position, closing the shutter. If at decisionblock 1210, it is determined that no state change is necessary for apixel 1102, the corresponding data interconnect 1106 is grounded.Although the relaxed position in this example is defined as theshutter-closed position, alternative shutter assemblies can be providedin which the relaxed state is a shutter-open position. In thesealternative cases, the application of data voltage V_(d), at step 1212,would result in the opening of the shutter.

In other implementations it is possible to apply the method 1200 of FIG.12 to a selected portion of the whole array of pixels, since it may beadvantageous to update different areas or groupings of rows and columnsin series. In this case a number of different charge triggerinterconnects 1112 could be routed to selected portions of the array forselectively updating and actuating different portions of the array.

As described above, to address the pixels 1102 in the control matrix1100, the data voltage V_(d) can be significantly less than theactuation voltage V_(at) (e.g., 5V vs. 40V). Since the actuation voltageV_(at) is applied once a frame, whereas the data voltage V_(d) may beapplied to each data interconnect 1106 as may times per frame as thereare rows in the control matrix 1100, control matrices such as controlmatrix 1100 may save a substantial amount of power in comparison tocontrol matrices which require a data voltage to be high enough to alsoserve as the actuation voltage.

For pixels 1102 in non-write-enabled rows, the bias voltage V_(b)applied to their corresponding scan-line interconnects 1104 keeps thepotential at their discharge transistor 1116 sources greater than thepotentials at their discharge transistor 1116 gate terminals, even whena data voltage V_(d) is applied to the data interconnect 1106 of theircorresponding columns. It will be understood that the embodiment of FIG.11 assumes the use of n-channel MOS transistors. Other embodiments arepossible that employ p-channel transistors, in which case the relativesigns of the bias potentials V_(b) and V_(d) would be reversed.

In other embodiments the discharge switch transistor 1116 can bereplaced by a set of two or more transistors, for instance if thecontrol matrix 1100 were to be built using standard CMOS technology thedischarge switch transistor could be comprised of a complementary pairof nMOS and pMOS transistors.

The method 1200 assumes digital information is written into an imageframe, i.e. where the shutters are intended to be either open or closed.Using the circuit of control matrix 1100, however, it is also possibleto write analog information into the shutter assemblies 1108. In thiscase, the grounding of the scan line interconnects is provided for onlya short and fixed amount of time and only partial voltages are appliedthrough the data line interconnects 1106. The application of partialvoltages to the discharge switch transistor 1116, when operated in alinear amplification mode, allows for only the partial discharge of theelectrode of the shutter assembly 1108 and therefore a partial openingof the shutter.

The control matrix 1100 selectively applies the data voltage to theremaining columns of the control matrix 1100 at the same time. After allpixels have achieved their intended states (step 1214), the controlmatrix 1100 reapplies V_(b) to the selected scan-line interconnect andselects a subsequent scan-line interconnect (step 1216). After allscan-lines have been addressed, the process begins again. As with thepreviously described control matrices, the activity of an attachedbacklight can be synchronized with the addressing of each frame.

FIG. 13 is a diagram of another control matrix 1300 suitable forinclusion in the display apparatus 100, according to an illustrativeembodiment of the invention. The control matrix 1300 is similar tocontrol matrix 1100, though pixels 1302 in the control matrix 1300include charge diodes 1304 as opposed to charge trigger switchtransistors 1114, and the control matrix 1300 lacks a charge triggerinterconnect 1112. More particularly, the control matrix 1300 includesone data interconnect 1306 for each column in the control matrix 1300and one scan-line interconnect 1308 for each row in the control matrix1300, and a discharge transistor 1309.

The control matrix 1300 also includes a charge interconnect 1310 (alsolabeled as V(at)) similar to that incorporated into control matrix 1100.

The control matrix 1300 includes a actuation voltage source electricallyconnected to the charge interconnect 1310. The actuation voltage sourcesupplies pulses of voltage at the beginning of each frame addressingcycle, allowing current to flow into the shutter assemblies 1314 of thepixels 1302 in the control matrix 1300 and thereby actuating anyunactuated actuators in the shutter assemblies 1314. As a result, afterthe voltage pulse, all of the pixels 1302 in the control matrix 1300 arein the same state, open or closed. After the voltage pulse, when thepotential of the charge interconnect 1310 has been reset to zero, thecharge diode 1304 prevents the voltage stored in the shutter assemblies1314 to be dissipated via the charge interconnect 1310. The controlmatrix 1300 can be controlled using a method similar to the pixeladdressing method 1200. Instead of applying a voltage to the chargetrigger interconnect 1112 at step 1202, the actuation voltage sourcesupplies a voltage pulse having duration and magnitude sufficient toopen any closed shutter assemblies.

It is preferable that the higher-capacitance electrode of shutterassemblies 1108 and 1314 be connected to the scan line interconnects1104 and 1308, while the lower-capacitance electrode be connectedthrough transistor 1114 or through diode 1304 to the chargeinterconnects 1112 or 1310. The voltage changes driven onto the shutterelectrodes through the charge interconnects will generally be higher inmagnitude than those experienced through the scan line interconnects.

FIG. 14 is a diagram of a control matrix 1400 suitable for inclusion inthe display apparatus 100. The control matrix 1400 includes thecomponents of control matrix 1300, i.e., scan-line interconnects 1402,data-interconnects 1404, and a charge interconnect 1406. The pixels 1408in the control matrix 1400 include a charge diode 1410, a shutterassembly 1412, and discharge transistor 1414. Control matrix 1400 alsoincludes a global actuation interconnect 1416 for providing globalactuation of the pixels 1408 in the control matrix 1400, using a methodsimilar to that described in relation to FIGS. 9 and 10. The controlmatrix also includes an optional capacitor 1418, which is connected inparallel with the source and drain of the discharge transistor 1414. Thecapacitor helps maintain a stable voltage at one electrode of shutterassembly 1412 despite voltage changes which might be applied on theother electrode through the global actuation interconnect 1416 Theinterconnect 1416 is shared among pixels 1408 in multiple rows andmultiple columns in the array.

The global actuation interconnect, if used in a mode similar to polarityreversal method 2 of Table 1, may be employed to ensure a 0V DC averagemode of operation in addition to providing an actuation thresholdvoltage. To achieve 0V DC averaging, the control matrix alternatesbetween control logics. In the first control logic, similar to thatemployed in the pixel addressing method 1000 and 1200, at the beginningof a frame addressing cycle, the control matrix 1400 opens the shutterassemblies 1412 of all pixels in the control matrix 1400 by storingV_(at) across the electrodes of the shutter assembly 1412 actuator. Thecontrol matrix 1400 then applies a bias voltage to lock the shutterassemblies 1412 in the open state. Control matrix 1400 applies a biasvoltage, e.g., ½ V_(at), which is greater than V_(m), via the globalactuation interconnect 1416. Then, to change the state of a shutterassembly 1412, when the row of pixels 1408 in which the shutter assembly1412 is located is write-enabled, the control matrix 1400 discharges thestored V_(at) in the shutter assembly 1412. The maintenance voltagekeeps the shutter assembly 1412 open until the global actuationinterconnect 1416 is grounded.

In the second control logic, which is similar to the polarity reversalmethod 2 of Table 1, instead of the control matrix changing the voltageapplied to the global actuation interconnect 1416 from ½ V_(at) toground, the control matrix changes the voltage applied to the globalactuation interconnect 1416 from ½ V_(at) to V_(at). Thus, to release ashutter in a shutter assembly 1412 to its relaxed state, the voltageapplied via the charge diode 1410 must be maintained, as opposed todischarged. Therefore, in the second control logic, the control matrix1400 discharges the stored V_(at) from shutter assemblies that are toremain open, as opposed to those that are closed. The control matrix1400 can alternate between the control logics every frame or on someother periodic basis. Over time, the net potentials applied across theactuators of the shutter assemblies 1408 by the charge interconnect 1406and the global actuation interconnect 1416 average out to 0V.

FIG. 15 is a diagram of still another suitable control matrix 1500 forinclusion in the display apparatus 100, according to an illustrativeembodiment of the invention. The control matrix 1500 is similar to thecontrol matrix 1100 of FIG. 11. Control matrix 1500 includes a datainterconnect 1502 for each column of pixels 1504 in the control matrix1500 and a scan-line interconnect 1506 for each row of pixels 1504 inthe control matrix 1500. The control matrix 1500 includes a commoncharge trigger interconnect 1508 and a common charge interconnect 1510.The pixels 1504 in the control matrix 1500 each include an elasticshutter assembly 1511, a charge trigger switch transistor 1512 and adischarge switch transistor 1514, as described in FIG. 11. Controlmatrix 1500 also incorporates a global actuation interconnect 1516 andits corresponding functionality described in FIG. 9 in relation tocontrol matrix 900. Control matrix 1500 also incorporates an optionalvoltage stabilizing capacitor 1517 which is connected in parallel withthe source and drain of discharge switch transistor 1514.

Each pixel 1504 of control matrix 1500, also includes a thirdtransistor, a write-enable transistor 1518, and a data store capacitor1520. The scan-line interconnect 1506 for a row of pixels 1504 connectsto the gates of the write-enable transistor 1518 incorporated into eachpixel 1504 in the row. The data interconnects 1502 for the columns ofthe control matrix 1500 electrically connect to the source terminals ofthe write-enable transistors 1518 of the pixels 1504 in the column. Thedrain of the write-enable transistors 1518 in each pixel 1504electrically connect in parallel to the data store capacitor 1520 andthe gate terminal of the discharge trigger transistor 1514 of therespective pixels 1504.

The operation of the control matrix 1500 includes elements in commonwith each of the methods 1000 and 1200. At the beginning of an frameaddressing cycle, a voltage is applied to the charge triggerinterconnect 1508 and the charge interconnect 1510 of the control matrix1500 to build up a potential, V_(at), on one shutter assembly 1511actuator electrode of each pixel 1504 in the control matrix 1500 to openany closed shutter assemblies 1511. These steps are similar to thoseperformed in steps 1202 and 1204 of FIG. 12. Each row is thenwrite-enabled in sequence, except instead of performing the write-enableas a grounding of corresponding scan-line interconnects as was done withrespect to FIGS. 11, 13, and 14, the control matrix 1500 applies awrite-enabling voltage V_(we) to the scan-line interconnect 1506corresponding to each row. While a particular row of pixels 1504 iswrite-enabled, the control matrix 1500 applies a data voltage to eachdata interconnect 1508 of the control matrix 1500 corresponding to acolumn that incorporates a pixel 1502 in the write-enabled row that isto be closed. The application of V_(we) to the scan-line interconnect1506 for the write-enabled row turns on the write-enable transistors1518 of the pixels 1504 in the corresponding scan line. The voltagesapplied to the data interconnects 1502 are thereby allowed to be storedon the data store capacitors 1520 of the respective pixels 1504.

If the voltage stored on the data store capacitor 1520 of a pixel 1504is sufficiently greater than ground, e.g., 5V, the discharge switchtransistor 1514 is activated, allowing the charge applied to thecorresponding shutter assembly 1511 via the charge trigger switchtransistor 1514 to discharge. The discharge of the larger voltage,V_(at), stored in the shutter assembly 1511, however, can take more timethan is needed to store the relatively small data voltage on the datastore capacitor 1520. By storing the data voltage on the data storecapacitor 1520, the discharge and the mechanical actuation process cancontinue even after the control matrix 1500 grounds the scan-lineinterconnect 1506, thereby isolating the charge stored on the capacitor1520 from its corresponding data interconnect 1502. In contrast to thedischarge process presented by the control matrices in FIGS. 11, 13, and14, therefore, the control matrix 1500 regulates the discharge switch1514 (for controlling application of the actuation voltage V_(at) onshutter assembly 1511) by means of data voltage which is stored on thecapacitor 1520, instead of requiring real time communication withsignals on the data interconnect 1502.

In alternative implementations, the storage capacitor 1520 andwrite-enable transistor 1518 can be replaced with alternative datamemory circuits, such as a DRAM or SRAM circuits known in the art.

In contrast to the circuits shown in FIGS. 11, 13, and 14, the charge onthe electrodes of shutter assembly 1511, when discharged, does not flowto ground by means of the scan line interconnect that corresponds topixel 1504. Instead the source of the discharge switch transistor 1514is connected to the scan line interconnect 1522 of the pixel in the rowbelow it. When not write-enabled the scan line interconnects 1522 incontrol matrix 1500 are held at or near to the ground potential; theycan thereby function as effective sinks for discharge currents inneighboring rows.

The control matrix 1500 also includes the capability for globalactuation, the process or method of which is similar to that describedin FIG. 10. The shutters in discharged pixels 1504 are kept in positiondue to the application of a maintenance voltage V_(m), e.g., ½ V_(at),to the global actuation interconnect 1516. After all rows have beenaddressed, the control matrix 1500 grounds the global actuationinterconnect 1516, thereby releasing the shutters of all dischargedshutter assemblies 1511 substantially in unison.

FIG. 16A is a diagram of still another suitable control matrix 1600 forinclusion in the display apparatus 100, according to an illustrativeembodiment of the invention. The control matrix 1600 is similar to thecontrol matrix 1500 of FIG. 15. Control matrix 1600 includes a datainterconnect 1602 for each column of pixels 1604 in the control matrix1600, a scan-line interconnect 1606 for each row of pixels 1604 in thecontrol matrix 1600. The control matrix 1600 includes a common chargetrigger interconnect 1608, a common charge interconnect 1610, and aglobal actuation interconnect 1612. The pixels 1604 in the controlmatrix 1600 each include an elastic shutter assembly 1614, a chargetrigger switch transistor 1616, a discharge switch transistor 1617, awrite-enable transistor 1618, and a data store capacitor 1620 asdescribed in FIG. 15. The control matrix 1600 also includes a shuttercommon interconnect 1622 which is distinct from the global actuationinterconnect 1612. These interconnects 1612 and 1622 are shared amongpixels 1604 in multiple rows and multiple columns in the array.

In operation the control matrix 1600 performs the same functions asthose of control matrix 1500, but by different means or methods. Mostparticularly, the method for accomplishing global actuation in controlmatrix 1600 is unique from that performed in control matrices 900, 1400,or 1500. In the previous methods, the global actuation interconnect wasconnected to one electrode of the shutter assembly, and applying amaintenance voltage V_(m) to it prevented shutter actuation. In controlmatrix 1600, however, the global actuation interconnect 1612 isconnected to the source of the discharge switch transistor 1617.Maintaining the global actuation interconnect 1612 at a potentialsignificantly above that of the shutter common interconnect 1622prevents the turn-on of any of the discharge switch transistors 1617,regardless of what charge is stored on capacitor 1620. Global actuationin control matrix 1600 is achieved by bringing the potential on theglobal actuation interconnect 1612 to the same potential as the shuttercommon interconnect 1622, making it possible for those discharge switchtransistors 1617 s to turn-on in accordance to the whether a datavoltage has been stored on capacitor 1620 or not. Control matrix 1600,therefore, does not depend on electrical bi-stability in the shutterassembly 1614 in order to achieve global actuation.

Applying partial voltages to the data store capacitor 1620 allowspartial turn-on of the discharge switch transistor 1617 during the timethat the global actuation interconnect 1612 is brought to its actuationpotential. In this fashion, an analog voltage is created on the shutterassembly 1614, for providing analog gray scale.

In the control matrix 1600, in contrast to control matrix 1500, thehigher-capacitance electrode of the actuators in the shutter assemblies1614 electrically connect to the shutter common interconnect 1622,instead of the global actuation interconnect 1612. In operation, thecontrol matrix alternates between two control logics as described inrelation to control matrix 1400 of FIG. 14. For control matrix 1600,however, when the control matrix switches between the control logics,the control matrix 1600 switches the voltage applied to the shuttercommon interconnect 1622 to either ground or V_(at), depending on theselected control logic, instead of switching the global actuationvoltage applied to the global actuation interconnect, as is done bycontrol matrix 1400.

As in the control matrix 1300 of FIG. 13, a simple diode and/or an MIMdiode can be substituted for the charge trigger transistor 1616 toperform the switching or charge loading function for each pixel in thearray.

FIG. 16B is yet another suitable control matrix 1640 for inclusion inthe display apparatus 100, according to an illustrative embodiment ofthe invention. Control matrix 1640 controls an array of pixels 1642 thatinclude elastic shutter assemblies. The control matrix 1640 includes asingle data interconnect 1648 for each column of pixels 1642 in thecontrol matrix. As such, the control matrix 1640 is suitable forcontrolling elastic shutter assemblies 1644, such as shutter assembly200. The actuators in the shutter assemblies 1644 can be made eitherelectrically bi-stable or mechanically bi-stable.

The control matrix 1640 includes a scan-line interconnect 1646 for eachrow of pixels 1642 in the control matrix 1640. The control matrix 1640further includes a charge interconnect 1650, and a global actuationinterconnect 1654, and a shutter common interconnect 1655. Theseinterconnects 1650, 1654 and 1655 are shared among pixels 1642 inmultiple rows and multiple columns in the array. In one implementation(the one described in more detail below), the interconnects 1650, 1654,and 1655 are shared among all pixels 1642 in the control matrix 1640.

Each pixel 1642 in the control matrix includes a shutter chargetransistor 1656, a shutter discharge transistor 1658, a shutterwrite-enable transistor 1657, and a data store capacitor 1659, asdescribed in FIGS. 16A and 19. Control matrix 1640 also incorporates anoptional voltage stabilizing capacitor 1652 which is connected inparallel with the source and drain of discharge switch transistor 1658.

By comparison to control matrix 1600, the charging transistor 1656 iswired with a different circuit connection to the charge interconnect1650. Control matrix 1640 does not include a charge trigger interconnectwhich is shared among pixels. Instead, the gate terminals of thecharging transistor 1656 are connected directly to the chargeinterconnect 1650, along with the drain terminal of transistor 1656. Inoperation, the charging transistors 1656 operate essentially as diodes,they can pass a current in only 1 direction. Their function in thecharging circuit becomes equivalent to that of diode 1410 in controlcircuit 1400 of FIG. 14.

At the beginning of each frame addressing cycle the control matrix 1640applies a voltage pulse to the charge interconnect 1650, allowingcurrent to flow through charging transistor 1656 and into the shutterassemblies 1644 of the pixels 1642. After this charging pulse, each ofthe shutter electrodes of shutter assemblies 1644 will be in the samevoltage state. After the voltage pulse, the potential of chargeinterconnect 1650 is reset to zero, and the charging transistors 1656will prevent the charge stored in the shutter assemblies 1644 from beingdissipated through charge interconnect 1650. The charge interconnect1650, in one implementation, transmits a pulsed voltage equal to orgreater than V_(at), e.g., 40V.

Each row is then write-enabled in sequence, as was described withrespect to control matrix 1500 of FIG. 15. While a particular row ofpixels 1642 is write-enabled, the control matrix 1640 applies a datavoltage to the data interconnect 1648 corresponding to each column ofpixels 1642 in the control matrix 1640. The application of V_(we) to thescan-line interconnect 1646 for the write-enabled row turns on thewrite-enable transistor 1657 of the pixels 1642 in the correspondingscan line. The voltages applied to the data interconnect 1648 is therebycaused to be stored on the data store capacitor 1659 of the respectivepixels 1642.

In control matrix 1640 the global actuation interconnect 1654 isconnected to the source of the shutter discharge switch transistor 1658.Maintaining the global actuation interconnect 1654 at a potentialsignificantly above that of the shutter common interconnect 1655prevents the turn-on of the discharge switch transistor 1658, regardlessof what charge is stored on the capacitor 1659. Global actuation incontrol matrix 1640 is achieved by bringing the potential on the globalactuation interconnect 1654 to ground or to substantially the samepotential as the shutter common interconnect 1655, enabling thedischarge switch transistor 1658 to turn-on in accordance to the whethera data voltage has been stored on capacitor 1659. Control matrix 1640,therefore, does not depend on electrical bi-stability in the shutterassembly 1644 in order to achieve global actuation.

Applying partial voltages to the data store capacitor 1659 allowspartial turn-on of the discharge switch transistor 1658 during the timethat the global actuation interconnect 1654 is brought to its actuationpotential. In this fashion, an analog voltage is created on the shutterassembly 1644, for providing analog gray scale.

An alternative method of addressing pixels in control matrix 1640 isillustrated by the method 1670 shown in FIG. 16C. The method 1670proceeds in three general steps. First the matrix is addressed row byrow by storing data into the data store capacitors 1659. Next allactuators are actuated (or reset) simultaneously (step 1688) be applyinga voltage V_(at) to the charge interconnect 1650. And finally the imageis set in a global actuation step 1692 by selectively activatingtransistors 1658 by means of the global actuation interconnect 1654.

In more detail, the frame addressing cycle of method 1670 begins when avoltage V_(off) is applied to the global actuation interconnect 1654(step 1672). The voltage V_(off) on interconnect 1654 is designed toensure that the discharge transistor 1658 will not turn on regardless ofwhether a voltage has been stored on capacitor 1659.

The control matrix 1640 then proceeds with the addressing of each pixel1642 in the control matrix, one row at a time (steps 1674-1684). Toaddress a particular row, the control matrix 1640 write-enables a firstscan line by applying a voltage V_(we) to the corresponding scan-lineinterconnect 1646 (step 1674). Then, at decision block 1676, the controlmatrix 1640 determines for each pixel 1642 in the write-enabled rowwhether the pixel 1642 needs to be open or closed. For example, if atthe reset step 1688 all shutters are to be (temporarily) closed, then atdecision block 1676 it is determined for each pixel 1642 in thewrite-enabled row whether or not the pixel is to be (subsequently)opened. If a pixel 1642 is to be opened, the control matrix 1640 appliesa data voltage V_(d), for example 5V, to the data interconnect 1648corresponding to the column in which that pixel 1642 is located (step1678). The voltage V_(d) applied to the data interconnect 1648 isthereby caused to be stored by means of a charge on the data storecapacitor 1659 of the selected pixel 1642 (step 1679). If at decisionblock 1676, it is determined that a pixel 1642 is to be closed, thecorresponding data interconnect 1648 is grounded (step 1680). Althoughthe relaxed position in this example is defined as the shutter-openposition, alternative shutter assemblies can be provided in which therelaxed state is a shutter-closed position. In these alternative cases,the application of data voltage V_(d), at step 1678, would result in theclosing of the shutter.

The application of V_(we) to the scan-line interconnect 1646 for thewrite-enabled row turns on all of the write-enable transistors 1657 forthe pixels 1642 in the corresponding scan line. The control matrix 1640selectively applies the data voltage to all columns of a given row inthe control matrix 1640 at the same time while that row has beenwrite-enabled. After all data has been stored on capacitors 1659 in theselected row (steps 1679 and 1681), the control matrix 1640 grounds theselected scan-line interconnect (step 1682) and selects a subsequentscan-line interconnect for writing (step 1685). After the informationhas been stored in the capacitors for all the rows in control matrix1640, the decision block 1684 is triggered to begin the global actuationsequence.

The actuation sequence begins at step 1686 of method 1670, with theapplication of an actuation voltage V_(at), e.g. 40 V, to the chargeinterconnect 1650. As a consequence of step 1686, the voltage V_(at) isnow imposed simultaneously across all the actuators of all the shutterassemblies 1644 in control matrix 1640. The control matrix 1640continues to apply the voltage V_(at) (step 1686) for a period of timesufficient for all actuators to actuate into an initial state (step1688). For the example given in method 1670, step 1688 acts to reset andclose all actuators. Alternatives to the method 1670 are possible,however, in which the reset step 1688 acts to open all shutters. At thenext step 1690 the control matrix grounds the charge interconnect 1650.A voltage, at least greater than a maintenance voltage V_(m), remainsstored across the capacitor 1652, thereby holding the shutters inposition. The electrodes on the actuators in shutter assembly 1644provide a capacitance which also stores a charge after the chargeinterconnect 1650 has been grounded, useful for those embodiments inwhich capacitor 1652 is not included.

After all actuators have been actuated and held in their closed positionby voltage in excess of V_(m), the data stored in capacitors 1659 cannow be utilized to set an image in control matrix 1640 by selectivelyopening the specified shutter assemblies (steps 1692 and 1694). First,the potential on the global actuation interconnect 1654 is set tosubstantially the same potential as the shutter common interconnect 1655(step 1692). Step 1692 makes it possible for the discharge switchtransistor 1658 to turn-on in accordance to whether a data voltage hasbeen stored on capacitor 1659. For those pixels in which a voltage hasbeen stored on capacitor 1659, the charge which was stored on theactuator of shutter assembly 1644 is now allowed to dissipate throughthe global actuation interconnect 1654. At step 1694, therefore,selected shutters are discharged through transistor 1658 and allowed toreturn by means of a restoring force or spring into their relaxedposition. For the example given in method 1670, a discharge into therelaxed position means that the selected shutter assemblies 1644 areplaced in their open position. For pixels where no voltage was stored oncapacitor 1659, the transistor 1658 remains closed at step 1694, nodischarge will occur and the shutter assembly 1644 remains closed.

To set an image in a subsequent video frame, the process begins again atstep 1672.

In the method 1670, all of the shutters are closed simultaneously duringthe time between step 1688 and step 1694, a time in which no imageinformation can be presented to the viewer. The method 1670, however, isdesigned to minimize this dead time (or reset time) by making use ofdata store capacitors 1659 and global actuation interconnect 1654 toprovide timing control over the transistors 1658. By the action of step1672, all of the data for a given image frame can be written to thecapacitors 1659 during the addressing sequence (steps 1674-1685),without any immediate actuation effect on the shutter assemblies. Theshutter assemblies 1644 remain locked in the positions they wereassigned in the previous image frame until addressing is complete andthey are uniformly actuated or reset at step 1688. The global actuationstep 1692 allows the simultaneous transfer of data out of the data storecapacitors 1659 so that all shutter assemblies can be brought into theirnext addressed image state at the same time.

As with the previously described control matrices, the activity of anattached backlight can be synchronized with the addressing of eachframe. To take advantage of the minimal dead time offered in theaddressing sequence of method 1670, a command to turn the illuminationoff can be given between step 1684 and step 1686. The illumination canthen be turned-on again after step 1694. In a field-sequential colorscheme, a lamp with one color can be turned off after step 1684 while alamp with either the same or a different color is turned on after step1694.

In other implementations it is possible to apply the method 1670 of FIG.16C to a selected portion of the whole array of pixels, since it may beadvantageous to update different areas or groupings of rows and columnsin series. In this case a number of different charge interconnects 1650and global actuation interconnects 1654 could be routed to selectedportions of the array for selectively updating and actuating differentportions of the array.

As described above, to address the pixels 1642 in the control matrix1640, the data voltage V_(d) can be significantly less than theactuation voltage V_(at) (e.g., 5V vs. 40V). Since the actuation voltageV_(at) is applied once a frame, whereas the data voltage V_(d) may beapplied to each data interconnect 1648 as may times per frame as thereare rows in the control matrix 1640, control matrices such as controlmatrix 1640 may save a substantial amount of power in comparison tocontrol matrices which require a data voltage to be high enough to alsoserve as the actuation voltage.

It will be understood that the embodiment of FIG. 16B assumes the use ofn-channel MOS transistors. Other embodiments are possible that employp-channel transistors, in which case the relative signs of the biaspotentials V_(at) and V_(d) would be reversed.

The method 1670 assumes digital information is written into an imageframe, i.e. where the shutters are intended to be either open or closed.Using the circuit of control matrix 1640, however, it is also possibleto write analog information into the shutter assemblies 1644. In thiscase, the grounding of the scan line interconnects is provided for onlya short and fixed amount of time and only partial voltages are appliedthrough the data line interconnects 1648. The application of partialvoltages to the discharge switch transistor 1658, when operated in alinear amplification mode, allows for only the partial discharge of theelectrode of the shutter assembly 1644 and therefore a partial openingof the shutter.

In operation, in order to periodically reverse the polarity of voltagessupplied to the shutter assembly 1644, the control matrix alternatesbetween two control logics, as described in relation to control matrix1400 of FIG. 14. In the first control logic, at step 1686 in theaddressing cycle, the control matrix 1640 closes the shutter assemblies1644 of all pixels in the control matrix 1640 by storing V_(at) acrossthe electrodes of the shutter assembly 1644 actuator. The potential onthe shutter common interconnect 1655 is held at ground.

In the second control logic, which is similar to the polarity reversalmethod 2 of Table 1 described with respect to FIG. 10, the potential ofthe shutter common interconnect 1655 is set instead to the actuationvoltage V_(at). At steps 1686 and 1688, where the voltage on the chargeinterconnect 1650 is set to V_(at), all shutters are instead allowed torelax to their open position. Therefore, in the second control logic,the control matrix 1640 discharges the stored V_(at) from shutterassemblies that are to be closed, as opposed to those that are to remainopen. At step 1692, global actuation is achieved by setting the globalactuation interconnect 1654 to ground.

The control matrix 1640 can alternate between the control logics everyframe or on some other periodic basis. Over time, the net potentialsapplied to the shutter assemblies 1644 by the charge interconnect 1650and the shutter common interconnect 1655 average out to 0V.

FIG. 17 is still a further suitable control matrix 1700 for inclusion inthe display apparatus 100, according to an illustrative embodiment ofthe invention. Control matrix 1700 controls an array of pixels 1702 thatinclude elastic shutter assemblies 1704. The control matrix 1700preferably includes shutter assemblies that are not bi-stable, so thatthe shutter assemblies 1704 are better controlled in an analog fashion.That is, the application of a particular voltage to the actuator of oneof the shutter assemblies 1704 results in a known incremental shutterdisplacement.

Control matrix 1700 includes one scan-line interconnect 1706 for eachrow of pixels 1702 in the control matrix 1700 and one data interconnect1708 for each column of pixels 1702 in the control matrix 1700. Thecontrol matrix 1700 also includes a charge interconnect 1710, a chargetrigger interconnect 1712, and a discharge trigger interconnect 1714.These interconnects 1710, 1712, and 1714 are shared amongst all or asubset of the pixels 1702 in the control matrix 1700. Each pixel 1702 inthe control matrix 1700 includes four transistors, a charge triggertransistor 1716, a grayscale transistor 1718, a discharge transistor1720, and a write-enable transistor 1722. The gate of the charge triggertransistor 1716 electrically connects to the charge trigger interconnect1712. Its drain electrically connects to the charge interconnect 1710,and its source electrically connects to the grayscale transistor 1718.The gate of the grayscale transistor 1718 electrically connects, inparallel, to a data store capacitor 1724 and the write-enable transistor1722. The source of the grayscale transistor 1718 electrically connectsto the discharge transistor 1720. The gate of the discharge transistor1720 electrically connects to the discharge interconnect 1714, and itssource is grounded. Referring back to the write-enabling transistor1722, its gate electrically connects to its corresponding scan-lineinterconnect 1706, and its drain electrically connects to itscorresponding data interconnect 1708.

The control matrix 1700 can be utilized to provide analog gray scale tothe display apparatus 100. In operation, at the beginning of a frameaddressing cycle, the control matrix 1700 applies a voltage to thedischarge trigger interconnect 1714, turning on the discharge transistor1720. Any voltage stored in the actuators of the shutter assemblies 1704in the pixels 1702 is discharged, releasing the shutters in the shutterassemblies 1704 to their rest positions. The control matrix 1700 thengrounds the discharge trigger interconnect 1714. Subsequently, thecontrol matrix 1700, in sequence applies a write-enabling voltage V_(we)to each scan-line interconnect 1706, turning on the write-enablingtransistors 1722 of the pixels 1702 in each corresponding row of thecontrol matrix 1700. As the write-enabling transistor 1722 for a givenrow is turned on, the control matrix 1700 applies voltage pulses to eachof the data-interconnects 1708 to indicate the desired brightness ofeach pixel 1702 in the write-enabled row of pixels 1702. After theaddressing sequence is complete, the control matrix then applies avoltage to the charge trigger interconnect 1712 which turns on thecharge trigger transistor 1716 so that all electrodes can be charged andall pixels actuated simultaneously.

Brightness of a pixel 1702 is determined by the duration or themagnitude of the voltage pulse applied to its corresponding datainterconnect 1708. While the voltage pulse is applied to the datainterconnect 1708 of the pixel, current flows through the write-enablingtransistor 1722, building up a potential on the data store capacitor1724. The voltage on the capacitor 1724 is used to control the openingof the conducting channel in the grayscale transistor 1718. This channelremains open so long as the gate-to-source voltage exceeds a certainthreshold voltage. Eventually, during the charging cycle, the potentialon the electrode of shutter assembly 1704 will rise to match thepotential stored on the capacitor 1724, at which point the grayscaletransistor will turn off. In this fashion the actuation voltage storedon the shutter assembly can be made to vary in proportion to the analogvoltage stored on capacitor 1724. The resulting electrode voltage causesan incremental displacement of the shutter in the shutter assembly 1704proportional to the resultant voltage. The shutter remains displacedfrom its rest position until the discharge trigger interconnect 1714 ispowered again at the end of the frame addressing cycle.

As in the control matrix 1300 of FIG. 13, a simple diode and/or an MIMdiode can be substituted for the charge trigger transistor 1716 toperform the switching or charge loading function for each pixel in thearray.

FIG. 18 is yet another suitable control matrix 1800 for inclusion in thedisplay apparatus 100, according to an illustrative embodiment of theinvention. Control matrix 1800 controls an array of pixels 1802 thatinclude dual-actuator shutter assemblies 1804 (i.e., shutter assemblieswith both shutter-open and shutter-close actuators). The actuators inthe shutter assemblies 1804 can be made either electrically bi-stable ormechanically bi-stable.

The control matrix 1800 includes a scan-line interconnect 1806 for eachrow of pixels 1802 in the control matrix 1800. The control matrix 1800also includes two data interconnects, a shutter-open interconnect 1808 aand a shutter-close interconnect 1808 b, for each column of pixels 1802in the control matrix 1800. The control matrix 1800 further includes acharge interconnect 1810, a charge trigger interconnect 1812, and aglobal actuation interconnect 1814. These interconnects 1810, 1812, and1814 are shared among pixels 1802 in multiple rows and multiple columnsin the array. In one implementation (the one described in more detailbelow), the interconnects 1810, 1812, and 1814 are shared among allpixels 1802 in the control matrix 1800.

Each pixel 1802 in the control matrix includes a shutter-open chargetransistor 1816, a shutter-open discharge transistor 1818, ashutter-close charge transistor 1820, and a shutter-close dischargetransistor 1822. The control matrix also incorporates two voltagestabilizing capacitors 1824, which are connected, one each, in parallelwith the source and drain of the discharge transistors 1818 and 1822. Atthe beginning of each frame addressing cycle, the control matrix 1800applies a maintenance voltage, V_(m), e.g., ½ the voltage needed toactuate the shutter assemblies, V_(at), to the global actuationinterconnect 1814. The maintenance voltage locks the shutter assemblies1804 into their current states until a global actuation is initiated atthe end of the frame addressing cycle. The control matrix 1800 thenapplies a voltage to the charge trigger interconnect 1812, turning onthe shutter-open and shutter-close transistors 1816 and 1820 of thepixels 1802 in the control matrix 1800. The charge interconnect 1810, inone implementation, carries a DC voltage equal to or greater thanV_(at), e.g., 40V.

As each row of pixels 1802 in the control matrix 1800 is addressed, thecontrol matrix 1800 write-enables a row of pixels 1802 by grounding itscorresponding scan-line interconnect 1806. The control matrix 1800 thenapplies a data voltage, V_(d), e.g., 5V, to either the shutter-openinterconnect 1808 a or the shutter-close interconnect 1808 bcorresponding to each column of pixels 1802 in the control matrix 1800.If V_(d) is applied to the shutter-closed interconnect 1808 b of acolumn, the voltage stored on the shutter-close actuator of thecorresponding shutter assembly 1804 is discharged via the shutter-closedischarge transistor 1822. Similarly if V_(d) is applied to theshutter-open interconnect 1808 a of a column, the voltage stored on theshutter-open actuator of the corresponding shutter assembly 1804 isdischarged via the shutter-open discharge transistor 1818. Generally, toensure proper actuation, only one of the actuators, either theshutter-closed actuator or the shutter-open actuator, is allowed to bedischarged for any given shutter assembly in the array.

After all rows of pixels 1802 are addressed, the control matrix 1800globally actuates the pixels 1802 by changing the potential on theglobal actuation interconnect 1814 from V_(m) to ground. The change involtage releases the actuators from their locked in state to switch totheir next state, if needed. If the global actuation interconnect wereto be replaced with a constant voltage ground or common interconnect,i.e. if the global actuation method is not utilized with the controlmatrix 1800, then the voltage stabilizing capacitors 1824 may not benecessary.

As in the control matrix 1400 of FIG. 14, a simple diode and/or an MIMdiode can be substituted for both the shutter-open charge transistor1816 and the shutter-close charge transistor 1820.

Alternatively, it is possible to take advantage of the bi-stable natureof shutter assembly 1804 and substitute a resistor for both theshutter-open charge transistor 1816 and the shutter-close chargetransistor 1820. When operated with a resistor, one relies on the factthat the RC charging time constant associated with the resistor and thecapacitance of the actuator in the shutter assembly 1804 can be muchgreater in magnitude than the time necessary for discharging theactuator through either the shutter-open discharge transistor 1818 orthe shutter-close discharge transistor 1822. In the time intervalbetween when the actuator of the shutter assembly 1804 is dischargedthrough one of the discharge transistors and when the actuator isre-charged through the resistor and the charge interconnect 1810, thecorrect voltage differences can be established across the actuators ofthe shutter assembly 1804 and the shutter assembly can be caused toactuate. After each of the open and closed actuators of the shutterassembly 1804 have been re-charged through the resistor, the shutterassembly 1804 will not re-actuate since either or both of the actuatorsnow effectively holds the appropriate maintenance voltage, i.e., avoltage greater than V_(m).

FIG. 19 is yet another suitable control matrix 1900 for inclusion in thedisplay apparatus 100, according to an illustrative embodiment of theinvention. Control matrix 1900 controls an array of pixels 1902 thatinclude dual-actuator shutter assemblies 1904 (i.e., shutter assemblieswith both shutter-open and shutter-close actuators). The actuators inthe shutter assemblies 1904 can be made either electrically bi-stable ormechanically bi-stable.

The control matrix 1900 includes a scan-line interconnect 1906 for eachrow of pixels 1902 in the control matrix 1900. The control matrix 1900also includes two data interconnects, a shutter-open interconnect 1908 aand a shutter-close interconnect 1908 b, for each column of pixels 1902in the control matrix 1900. The control matrix 1900 further includes acharge interconnect 1910, a charge trigger interconnect 1912, and aglobal actuation interconnect 1914, and a shutter common interconnect1915. These interconnects 1910, 1912, 1914 and 1915 are shared amongpixels 1902 in multiple rows and multiple columns in the array. In oneimplementation (the one described in more detail below), theinterconnects 1910, 1912, 1914 and 1915 are shared among all pixels 1902in the control matrix 1900.

Each pixel 1902 in the control matrix includes a shutter-open chargetransistor 1916, a shutter-open discharge transistor 1918, ashutter-open write-enable transistor 1917, and a data store capacitor1919 as described in FIG. 16A. Each pixel 1902 in the control matrixincludes a shutter-close charge transistor 1920, and a shutter-closedischarge transistor 1922, a shutter-close write-enable transistor 1927,and a data store capacitor 1929.

At the beginning of each frame addressing cycle the control matrix 1900applies a voltage to the charge trigger interconnect 1912, turning onthe shutter-open and shutter-close transistors 1916 and 1920 of thepixels 1902 in the control matrix 1900. The charge interconnect 1910, inone implementation, carries a DC voltage equal to or greater thanV_(at), e.g., 40V.

Each row is then write-enabled in sequence, as was described withrespect to control matrix 1500 of FIG. 15. While a particular row ofpixels 1902 is write-enabled, the control matrix 1900 applies a datavoltage to either the shutter-open interconnect 1908 a or theshutter-close interconnect 1908 b corresponding to each column of pixels1902 in the control matrix 1900. The application of V^(we) to thescan-line interconnect 1906 for the write-enabled row turns on both ofthe write-enable transistors 1917 and 1927 of the pixels 1902 in thecorresponding scan line. The voltages applied to the data interconnects1908 a and 1908 b are thereby allowed to be stored on the data storecapacitors 1919 and 1929 of the respective pixels 1902. Generally, toensure proper actuation, only one of the actuators, either theshutter-closed actuator or the shutter-open actuator, is allowed to bedischarged for any given shutter assembly in the array.

In control matrix 1900 the global actuation interconnect 1914 isconnected to the source of the both the shutter-open discharge switchtransistor 1918 and the shutter-close discharge transistor 1922.Maintaining the global actuation interconnect 1914 at a potentialsignificantly above that of the shutter common interconnect 1915prevents the turn-on of any of the discharge switch transistors 1918 or1922, regardless of what charge is stored on the capacitors 1919 and1929. Global actuation in control matrix 1900 is achieved by bringingthe potential on the global actuation interconnect 1914 to the samepotential as the shutter common interconnect 1915, making it possiblefor the discharge switch transistors 1918 or 1922 to turn-on inaccordance to the whether a data voltage has been stored on ethercapacitor 1919 or 1920. Control matrix 1900, therefore, does not dependon electrical bi-stability in the shutter assembly 1904 in order toachieve global actuation.

Applying partial voltages to the data store capacitors 1919 and 1921allows partial turn-on of the discharge switch transistors 1918 and 1922during the time that the global actuation interconnect 1914 is broughtto its actuation potential. In this fashion, an analog voltage iscreated on the shutter assembly 1904, for providing analog gray scale.

In operation, the control matrix alternates between two control logicsas described in relation to control matrix 1600 of FIG. 16A.

As in the control matrix 1300 of FIG. 13, simple MIM diodes or varistorscan be substituted for the charge trigger transistor 1616 to perform theswitching or charge loading function for each pixel in the array. Also,as in control matrix 1800 of FIG. 18 it is possible to substitute aresistor for both the shutter-open charge transistor 1916 and theshutter-close charge transistor 1920.

FIG. 20 is yet another suitable control matrix 2000 for inclusion in thedisplay apparatus 100, according to an illustrative embodiment of theinvention. Control matrix 2000 controls an array of pixels 2002 thatinclude dual-actuator shutter assemblies 2004 (i.e., shutter assemblieswith both shutter-open and shutter-close actuators). The actuators inthe shutter assemblies 2004 can be made either electrically bi-stable ormechanically bi-stable.

The control matrix 2000 includes a scan-line interconnect 2006 for eachrow of pixels 2002 in the control matrix 2000. The control matrix 2000also includes two data interconnects, a shutter-open interconnect 2008 aand a shutter-close interconnect 2008 b, for each column of pixels 2002in the control matrix 2000. The control matrix 2000 further includes acharge interconnect 2010, and a global actuation interconnect 2014, anda shutter common interconnect 2015. These interconnects 2010, 2014 and2015 are shared among pixels 2002 in multiple rows and multiple columnsin the array. In one implementation (the one described in more detailbelow), the interconnects 2010, 2014 and 2015 are shared among allpixels 2002 in the control matrix 2000.

Each pixel 2002 in the control matrix includes a shutter-open chargetransistor 2016, a shutter-open discharge transistor 2018, ashutter-open write-enable transistor 2017, and a data store capacitor2019 as described in FIGS. 16A and 19. Each pixel 2002 in the controlmatrix includes a shutter-close charge transistor 2020, and ashutter-close discharge transistor 2022, a shutter-close write-enabletransistor 2027, and a data store capacitor 2029.

Control matrix 2000 also incorporates two voltage stabilizing capacitors2031 and 2033 which connect on one side to the sources of the dischargeswitch transistors 2018 and 2022, respectively, and on the other side tothe shutter common interconnect 2015.

By comparison to control matrix 1900, the charging transistors 2016 and2020 are wired in with a different circuit connection to the chargeinterconnect 2010. Control matrix 2000 does not include a charge triggerinterconnect which is shared among pixels. Instead, the gate terminalsof both charging transistors 2016 and 2020 are connected directly to thecharge interconnect 2010, along with the drain terminal of transistors2016 and 2020. In operation, the charging transistors operateessentially as diodes, i.e., they can pass a current in only 1direction. Their function in the charging circuit becomes equivalent tothat of diode 1410 in control circuit 1400 of FIG. 14.

At the beginning of each frame addressing cycle the control matrix 2000applies a voltage pulse to the charge interconnect 2010, allowingcurrent to flow through charging transistors 2016 and 2020 and into theshutter assemblies 2004 of the pixels 2002. After this charging pulse,each of the shutter open and shutter closed electrodes of shutterassemblies 2004 will be in the same voltage state. After the voltagepulse, the potential of charge interconnect 2010 is reset to zero, andthe charging transistors 2016 and 2020 will prevent the charge stored inthe shutter assemblies 2004 from being dissipated through chargeinterconnect 2010. The charge interconnect 2010, in one implementation,transmits a pulsed voltage equal to or greater than V_(at), e.g., 40V.

Each row is then write-enabled in sequence, as was described withrespect to control matrix 1500 of FIG. 15. While a particular row ofpixels 2002 is write-enabled, the control matrix 2000 applies a datavoltage to either the shutter-open interconnect 2008 a or theshutter-close interconnect 2008 b corresponding to each column of pixels2002 in the control matrix 2000. The application of V_(we) to thescan-line interconnect 2006 for the write-enabled row turns on both ofthe write-enable transistors 2017 and 2027 of the pixels 2002 in thecorresponding scan line. The voltages applied to the data interconnects2008 a and 2008 b are thereby caused to be stored on the data storecapacitors 2019 and 2029 of the respective pixels 2002. Generally, toensure proper actuation, only one of the actuators, either theshutter-closed actuator or the shutter-open actuator, is caused to bedischarged for any given shutter assembly in the array.

In control matrix 2000 the global actuation interconnect 2014 isconnected to the source of the both the shutter-open discharge switchtransistor 2018 and the shutter-close discharge transistor 2022.Maintaining the global actuation interconnect 2014 at a potentialsignificantly above that of the shutter common interconnect 2015prevents the turn-on of any of the discharge switch transistors 2018 or2022, regardless of what charge is stored on the capacitors 2019 and2029. Global actuation in control matrix 2000 is achieved by bringingthe potential on the global actuation interconnect 2014 to substantiallythe same potential as the shutter common interconnect 2015, making itpossible for the discharge switch transistors 2018 or 2022 to turn-on inaccordance to whether a data voltage has been stored on ether capacitor2019 or 2029. Control matrix 2000, therefore, does not depend onelectrical bi-stability in the shutter assembly 2004 in order to achieveglobal actuation.

Applying partial voltages to the data store capacitors 2019 and 2021allows partial turn-on of the discharge switch transistors 2018 and 2022during the time that the global actuation interconnect 2014 is broughtto its actuation potential. In this fashion, an analog voltage iscreated on the shutter assembly 2004, for providing analog gray scale.

In operation, in order to periodically reverse the polarity of voltagessupplied to the shutter assembly 2004, the control matrix 2000alternates between two control logics, as described in relation tocontrol matrix 1600 of FIG. 16A.

FIG. 21 is yet another suitable control matrix 2100 for inclusion in thedisplay apparatus 100, according to an illustrative embodiment of theinvention. Control matrix 2100 controls an array of pixels 2102 thatinclude dual-actuator shutter assemblies 2104 (i.e., shutter assemblieswith both shutter-open and shutter-close actuators). The actuators inthe shutter assemblies 2104 can be made either electrically bi-stable ormechanically bi-stable.

The control matrix 2100 includes a scan-line interconnect 2106 for eachrow of pixels 2102 in the control matrix 2100. Despite the fact thatshutter assemblies 2104 are dual-actuator shutter assemblies, thecontrol matrix 2100 only includes a single data interconnect 2108. Thecontrol matrix 2100 further includes a charge interconnect 2110, and aglobal actuation interconnect 2114, and a shutter common interconnect2115. These interconnects 2110, 2114 and 2115 are shared among pixels2102 in multiple rows and multiple columns in the array. In oneimplementation (the one described in more detail below), theinterconnects 2110, 2114, and 2115 are shared among all pixels 2102 inthe control matrix 2100.

Each pixel 2102 in the control matrix includes a shutter-open chargetransistor 2116, a shutter-open discharge transistor 2118, ashutter-open write-enable transistor 2117, and a data store capacitor2119, as described in FIGS. 16A and 19. Each pixel 2102 in the controlmatrix includes a shutter-close charge transistor 2120, a shutter-closedischarge transistor 2122, and a data store capacitor 2129.

In addition and in contrast to control matrices described until now, thecontrol matrix 2100 includes a data load transistor 2135 and a datadischarge transistor 2137. Control matrix 2100 also incorporates twovoltage stabilizing capacitors 2131 and 2133 which connect on one sideto the sources of the discharge switch transistors 2118 and 2122,respectively, and on the other side to the shutter common interconnect2115.

The charging transistors 2116 and 2120 are wired similarly to that ofthe charging transistors in control matrix 2000 of FIG. 20. That is, thegate terminals of both charging transistors 2116 and 2120 are connecteddirectly to the charge interconnect 2110, along with the drain terminalof transistors 2116 and 2120. Their function in the charging circuitbecomes equivalent to that of diode 1410 in control circuit 1400 of FIG.14.

At the beginning of each frame addressing cycle the control matrix 2100applies a voltage pulse to the charge interconnect 2110, allowingcurrent to flow through charging transistors 2116 and 2120 and into theshutter assemblies 2104 of the pixels 2102. After this charging pulse,each of the shutter open and shutter closed electrodes of shutterassemblies 2104 will be in the same voltage state. After the voltagepulse, the potential of charge interconnect 2110 is reset to zero, andthe charging transistors 2116 and 2120 will prevent the charge stored inthe shutter assemblies 2104 from being dissipated through chargeinterconnect 2110. The charge interconnect 2110, in one implementation,transmits a pulsed voltage equal to or greater than V_(at), e.g., 40V.

Each row is then write-enabled in sequence, as was described withrespect to control matrix 1500 of FIG. 15. While a particular row ofpixels 2102 is write-enabled, the control matrix 2100 applies a datavoltage to the data interconnect 2108. The application of V_(we) to thescan-line interconnect 2106 for the write-enabled row turns on thewrite-enable transistor 2117 of the pixels 2102 in the correspondingscan line. The voltages applied to the data interconnect 2108 is therebycaused to be stored on the data store capacitor 2119 of the respectivepixels 2102. The same V_(we) that is applied to the write enabletransistor 2117 is applied simultaneously to both the gate and the drainof data load transistor 2135, which allows current to pass through thedata load transistor 2135 depending on whatever voltage is stored oncapacitor 2129.

The combination of transistors 2135 and 2137 functions essentially as aninverter with respect to the data stored on capacitor 2119. The sourceof data load transistor 2135 is connected to the drain of data dischargetransistor 2137 and simultaneously to an electrode of the data storecapacitor 2129. The gate of data discharge transistor 2137 is connectedto an electrode of data store capacitor 2119. The voltage stored oncapacitor 2129, therefore, becomes the complement or inverse of thevoltage stored on data store capacitor 2119. For instance, if thevoltage on the data store capacitor 2119 is V_(on), then the datadischarge transistor 2137 can switch on and the voltage on the datastore capacitor 2129 can become zero. Conversely, if the voltage on datastore capacitor 2119 is zero, then the data discharge transistor 2137will switch off and the voltage on the data store capacitor 2129 willremain at its pre-set voltage V_(we).

In control matrix 2100 the global actuation interconnect 2114 isconnected to the source of the shutter-open discharge switch transistor2118, the shutter-close discharge transistor 2122, and the datadischarge transistor 2137. Maintaining the global actuation interconnect2114 at a potential significantly above that of the shutter commoninterconnect 2115 prevents the turn-on of any of the discharge switchtransistors 2118, 2122 and 2137, regardless of what charge is stored onthe capacitors 2119. Global actuation in control matrix 2100 is achievedby bringing the potential on the global actuation interconnect 2114 tosubstantially the same potential as the shutter common interconnect2115. During the time that the global actuation is so activated, allthree of the transistors 2118, 2122, and 2137 can change their state,depending on what data voltage has been stored on capacitor 2119.Because of the operation of the inverter 2135 and 2137, only one of thedischarge transistors 2118 or 2122 can be on at any one time, ensuringproper actuation of shutter assembly 2104. The presence of the inverter2135 and 2137 helps to obviate the need for a separate shutter-closedata interconnect.

Applying partial voltages to the data store capacitors 2119 and 2129allows partial turn-on of the discharge switch transistors 2118 and 2122during the time that the global actuation interconnect 2114 is broughtto its actuation potential. In this fashion, an analog voltage iscreated on the shutter assembly 2104, for providing analog gray scale.

In operation, in order to periodically reverse the polarity of voltagessupplied to the shutter assembly 2104, the control matrix 2100alternates between two control logics as described in relation tocontrol matrix 1600 of FIG. 16A.

FIG. 22 is yet another suitable control matrix 2200 for inclusion in thedisplay apparatus 100, according to an illustrative embodiment of theinvention. Control matrix 2200 controls an array of pixels 2202 thatinclude dual-actuator shutter assemblies 2204 (i.e., shutter assemblieswith both shutter-open and shutter-close actuators). The actuators inthe shutter assemblies 2204 can be made either electrically bi-stable ormechanically bi-stable.

The control matrix 2200 includes a scan-line interconnect 2206 for eachrow of pixels 2202 in the control matrix 2200. The control matrix 2200also includes two data interconnects, a shutter-open interconnect 2208 aand a shutter-close interconnect 2208 b, for each column of pixels 2202in the control matrix 2200. The control matrix 2200 further includes acharge interconnect 2210, a global actuation interconnect 2214, and ashutter common interconnect 2215. These interconnects 2210, 2214 and2215 are shared among pixels 2202 in multiple rows and multiple columnsin the array. In one implementation (the one described in more detailbelow), the interconnects 2210, 2214 and 2215 are shared among allpixels 2202 in the control matrix 2200.

Each pixel 2202 in the control matrix includes a shutter-open chargetransistor 2216, a shutter-open discharge transistor 2218, ashutter-open write-enable transistor 2217, and a data store capacitor2219 as described in FIGS. 16A and 19. Each pixel 2202 in the controlmatrix includes a shutter-close charge transistor 2220, and ashutter-close discharge transistor 2222, a shutter-close write-enabletransistor 2227, and a data store capacitor 2229.

The control matrix 2200 makes use of two complementary types oftransistors, both p-channel and n-channel transistors. It is thereforereferred to as a complementary MOS control matrix or a CMOS controlmatrix. The charging transistors 2216 and 2220 are of the pMOS typewhile the discharge transistors 2218 and 2222 are of the nMOS type. Inother implementations, the types of transistors can be reversed, forexample nMOS transistors can be used for the charging transistors andpMOS transistors can be used for the discharge transistors. (The symbolfor a pMOS transistor includes an arrow that points into the channelregion, the symbol for an nMOS transistor includes an arrow that pointsaway from the channel region.)

The CMOS control matrix 2200 does not incorporate and does not requireany voltage stabilizing capacitors, such as 2031 and 2033 from controlmatrix 2000 of FIG. 20. Control matrix 2200 does not include a chargetrigger interconnect (such as charge trigger interconnect 1912 incontrol matrix 1900 of FIG. 19). By comparison to control matrices 1900and 2000, the charging transistors 2216 and 2220 are wired withdifferent circuit connections between the charge interconnect 2210 andthe shutter assembly 2204. The source of each of transistors 2216 and2220 are connected to the charge interconnect 2210. The gate ofshutter-close charge transistor 2220 is connected to the drain of ashutter-open discharge transistor 2218 and simultaneously to theshutter-open actuator of the corresponding shutter assembly 2204. Thegate of shutter-open charge transistor 2216 is connected to the drain ofa shutter-close discharge transistor 2222 and simultaneously to theshutter-close actuator of the corresponding shutter assembly 2204. Thedrain of shutter-close charge transistor 2220 is connected to the drainof a shutter-close discharge transistor 2222 and simultaneously to theshutter-close actuator of the corresponding shutter assembly 2204. Thedrain of shutter-open charge transistor 2216 is connected to the drainof a shutter-open discharge transistor 2218 and simultaneously to theshutter-open actuator of the corresponding shutter assembly 2204.

The operation of control matrix 2200 is distinct from that of thecircuits already discussed, in particular from control matrices 1800,1900, and 2000 of FIGS. 18, 19 and 20, respectively, which havegenerally employed the charging sequence described in control method1200 of FIG. 12. In control method 1200, as applied to control matrix1900, an actuation voltage is first applied to each side of the shutterassembly 1902, or applied simultaneously to the shutter-open actuatorand the shutter-closed actuators of shutter assembly 1902. Later, aspart of the global actuation sequence, either one actuator or the otherin shutter assembly 1902 is caused to discharge in accordance to whethera data voltage was stored on ether capacitor 1919 or 1929. By contrast,the operation of control matrix 2200 does not require a distinct orinitializing charging sequence. The charge interconnect 2210 ismaintained at a steady DC voltage equal to the actuation voltage V_(at),e.g. at 40 volts.

The control matrix 2200 operates as a logical flip-flop, which has onlytwo stable states. In the first stable state the shutter-open dischargetransistor 2218 is on, the shutter-closed discharge transistor 2222 isoff, the shutter-open charge transistor 2216 is off, and theshutter-close charge transistor 2220 is on. In this first stable statethe shutter-open actuator is discharged or set to the same potential asthe global actuation interconnect 2214, while the shutter-closedactuator is held at the actuation voltage V_(at). In the second stablestate the shutter-open discharge transistor 2218 is off, theshutter-closed discharge transistor 2222 is on, the shutter-open chargetransistor 2216 is on, and the shutter-close charge transistor 2220 isoff. In this second stable state the shutter-closed actuator isdischarged or set to the same potential as the global actuationinterconnect 2214, while the shutter-closed actuator is held at theactuation voltage V_(at). The cross-coupling of transistors 2216, 2218,2220, and 2222 helps to ensure that if any one of these 4 transistors ison—then only the two states described above can result as a stablestate. In various embodiments, the flip-flop can also be used to storepixel addressing data.

Those skilled in the art will recognize that both the shutter-open andshutter-close actuators of shutter assembly 2204 are connected to theoutput stage of a corresponding CMOS inverter. These inverters can belabeled as the shutter open inverter which comprises transistors 2216and 2218 and the shutter close inverter which comprises transistors 2220and 2222. The flip-flop operation of the switching circuit is formedfrom the cross-coupling of the two inverters. These inverters are alsoknown as level shifting inverters since the input voltages, from datastore capacitors 2219 and 2229, are lower than the output voltages, i.e.the V_(at) which is supplied to the actuators.

The two stable actuation states of control matrix 2200 are associatedwith substantially zero current flow between the charge interconnect2210 and the global actuation interconnect 2214, an important powersavings. This is achieved because the shutter-open charge transistor2216 and the shutter-close discharge transistor 2218 are made fromdifferent transistor types, pMOS or nMOS, while the shutter-close chargetransistor 2220 and the shutter-close discharge transistor 2222 are alsomade from the different transistor types, pMOS and nMOS.

The flip-flop operation of control matrix 2200 allows for a constantvoltage actuation of the shutter assembly 2204, without the need forvoltage stabilizing capacitors, such as capacitor 2031 or 2033 incontrol matrix 2000 of FIG. 20. This is because one of the chargingtransistors 2216 or 2220 remains on throughout the actuation event,allowing the corresponding actuator to maintain a low impedanceconnection to the DC supply of the interconnect 2210 throughout theactuation event.

At the beginning of each frame addressing cycle the control matrix 2200applies a write enable voltage to each scan-line interconnect 2206 insequence. While a particular row of pixels 2202 is write-enabled, thecontrol matrix 2200 applies a data voltage to either the shutter-openinterconnect 2208 a or the shutter-close interconnect 2208 bcorresponding to each column of pixels 2202 in the control matrix 2200.The application of V, to the scan-line interconnect 2206 for thewrite-enabled row turns on both of the write-enable transistors 2217 and2227 of the pixels 2202 in the corresponding scan line. The voltagesapplied to the data interconnects 2208 a and 2208 b are thereby causedto be stored on the data store capacitors 2219 and 2229 of therespective pixels 2202. Generally, to ensure proper actuation, only oneof the actuators, either the shutter-closed actuator or the shutter-openactuator, is caused to be discharged for any given shutter assembly inthe array.

In control matrix 2200 the global actuation interconnect 2214 isconnected to the source of the both the shutter-open discharge switchtransistor 2218 and the shutter-close discharge transistor 2222.Maintaining the global actuation interconnect 2214 at a potentialsignificantly above that of the shutter common interconnect 2215prevents the turn-on of any of the discharge switch transistors 2218 or2222, regardless of what charge is stored on the capacitors 2219 and2229. Global actuation in control matrix 2200 is achieved by bringingthe potential on the global actuation interconnect 2214 to substantiallythe same potential as the shutter common interconnect 2215, making itpossible for the discharge switch transistors 2218 or 2222 to turn-on inaccordance to whether a data voltage has been stored on either capacitor2219 or 2222. Upon setting the global actuation interconnect to the samepotential as the shutter common interconnect, the state of thetransistors will either remain unchanged from its stable state as it wasset at the last actuation event, or it will switch to the alternatestable state, in accordance to whether a data voltage has been stored oneither capacitor 2219 or 2222.

The voltage stored on capacitors 2219 or 2229 is not necessarily thesame as the actuation voltage as applied to the charge interconnect2210. Therefore some optional specifications on the transistors can helpto reduce any transient switching currents in control matrix 2200. Forinstance, it may be preferable to increase the ratio of width to lengthin the discharge transistors 2218 and 2222 as compared to the chargetransistors 2216 and 2220. The ratio of width to length for thedischarge transistors may vary between 1 to 10 while the ratio of lengthto width for the charge transistors may vary between 0.1 and 1.

In operation, in order to periodically reverse the polarity of voltagessupplied to the shutter assembly 2204, the control matrix 2200alternates between two control logics as described in relation tocontrol matrix 1600 of FIG. 16A.

FIG. 23 is yet another suitable control matrix 2300 for inclusion in thedisplay apparatus 100, according to an illustrative embodiment of theinvention. Control matrix 2300 controls an array of pixels 2302 thatinclude dual-actuator shutter assemblies 2304 (i.e., shutter assemblieswith both shutter-open and shutter-close actuators). The actuators inthe shutter assemblies 2304 can be made either electrically bi-stable ormechanically bi-stable.

The control matrix 2300 includes a scan-line interconnect 2306 for eachrow of pixels 2302 in the control matrix 2300. Despite the fact thatshutter assemblies 2304 are dual-actuator shutter assemblies, thecontrol matrix 2300 only includes a single data interconnect 2308. Thecontrol matrix 2300 further includes a charge interconnect 2310, and aglobal actuation interconnect 2314, and a shutter common interconnect2315. These interconnects 2310, 2314 and 2315 are shared among pixels2302 in multiple rows and multiple columns in the array. In oneimplementation (the one described in more detail below), theinterconnects 2310, 2314 and 2315 are shared among all pixels 2302 inthe control matrix 2300.

Each pixel 2302 in the control matrix includes a shutter-open chargetransistor Q16, a shutter-open discharge transistor Q18, a shutter-openwrite-enable transistor Q17, and a data store capacitor C19, asdescribed in FIGS. 16A and 19. Each pixel 2302 in the control matrixincludes a shutter-close charge transistor Q20, and a shutter-closedischarge transistor Q22, and a shutter-close write-enable transistorQ27.

The control matrix 2300 makes use of two complementary types oftransistors, both p-channel and n-channel transistors. It is thereforereferred to as a complementary MOS control matrix or a CMOS controlmatrix. The charging transistors Q16 and Q20, for instance, are of thepMOS type, while the discharge transistors Q18 and Q22 are of the nMOStype. In other implementations, the types of transistors employed incontrol matrix 2300 can be reversed, for example nMOS transistors can beused for the charging transistors and pMOS transistors can be used forthe discharge transistors.

In addition to the transistors identified above, the control matrix 2300includes a level shifting inverter 2332, comprised of transistors Q31and Q33; it includes a transition-sharpening inverter 2336, comprised oftransistors Q35 and Q37; and it includes a switching inverter 2340,comprised of transistors Q39 and Q41. Each of these inverters iscomprised of complementary pairs of transistors (i.e., nMOS coupled withpMOS). The sources of transistors Q33, Q37, and Q41 are connected to aV_(dd) supply interconnect 2334. The sources of transistors Q31, Q35,and Q39 are connected to the global actuation interconnect 2314.

The CMOS control matrix 2300 does not incorporate and does not requireany voltage stabilizing capacitors, such as 2031 and 2033 from controlmatrix 2000 of FIG. 20. Control matrix 2300 does not include a chargetrigger interconnect (such as charge trigger interconnect 1912 of FIG.19).

In a wiring similar to control matrix 2200, the transistors Q16, Q18,Q20, and Q22 are cross connected and operate as a flip flop. The sourcesof both transistors Q16 and Q20 are connected directly to chargeinterconnect 2310, which is held at a DC potential equal to theactuation voltage V_(at), e.g. at 40 volts. The sources of bothtransistors Q18 and Q22 are connected to the global actuationinterconnect 2314. The cross coupling of transistors Q16, Q18, Q20, andQ22 ensures that there are only two stable states—in which only one ofthe actuators in shutter assembly 2304 is held at the actuation voltageV_(at), while the other actuator (after global actuation) is held at avoltage near to zero. By contrast to the operation of control matrices1800, 1900, or 2000 of FIGS. 18, 19, and 20, respectively, the controlmatrix 2300 does not require a distinct charging sequence or anyvariation or pulsing of the voltage from charge interconnect 2310.

As was the case in control matrix 2200 of FIG. 22, the flip-flopswitching circuit can be recognized as the cross coupling of twoinverters, namely a shutter open inverter (transistors Q16 and Q18) anda shutter close inverter (transistors Q20 and Q22).

In either of its stable states, the flip-flop circuit formed bytransistors Q16, Q18, Q20, and Q22 is associated with substantially zeroDC current flow, and therefore forms a low power voltage switchingcircuit. This is achieved because of the use of complementary (CMOS)transistor types.

The flip-flop operation of control matrix 2300 allows for a constantvoltage actuation of the shutter assembly 2304, without the need forvoltage stabilizing capacitors, such as capacitor 2031 or 2033 incontrol matrix 2000 of FIG. 20. This is because one of the chargingtransistors Q16 or Q20 remains on throughout the actuation event,allowing the corresponding actuator to maintain a low impedanceconnection to the DC supply of the interconnect 2210 throughout theactuation event.

At the beginning of each frame addressing cycle the control matrix 2300applies a write enable voltage to each scan-line interconnect 2306 insequence. While a particular row of pixels 2302 is write-enabled, thecontrol matrix 2300 applies a data voltage to the data interconnect2308. The application of V, to the scan-line interconnect 2306 for thewrite-enabled row turns on the write-enable transistor Q17 of the pixels2302 in the corresponding scan line. The voltages applied to the datainterconnect 2308 is thereby caused to be stored on the data storecapacitor 2319 of the respective pixels 2302.

The functions of the inverters with transistors Q31 through Q41 will nowbe explained. The level shifting inverter 2332 outputs a voltage V_(dd)(derived from supply interconnect 2334), e.g. 8 volts, which isprovisionally supplied to the input of the transition sharpeninginverter 2336, depending on the voltage state of capacitor C19. Thetransition-sharpening inverter 2336 outputs the inverse or complement ofits input from the voltage leveling inverter 2332, and supplies thatcomplement voltage to both the switching inverter 2340, as well as tothe gate of transistor Q22. (By complement we mean that if the output ofthe voltage leveling inverter is V_(dd), then the output of thetransition sharpening inverter will be near to zero, and vice versa.)The output of the switching inverter 2340 supplies a voltage to the gateof transistor Q18, which is again the complement of the voltage suppliedfrom the transition-sharpening inverter 2336.

In a manner similar to the function of transistors 2135 and 2137 fromcontrol matrix 2100 of FIG. 21, the switching inverter 2340 ensures thatonly one of the discharge transistors Q18 or Q22 can be on at any onetime, thereby ensuring proper actuation of shutter assembly 2304. Thepresence of the switching inverter 2340 obviates the need for a separateshutter-close data interconnect.

The level shifting inverter 2332 requires only a low voltage input (e.g.3 volts) and outputs a complement which is shifted to the higher voltageof V_(dd) (e.g. 8 volts). For instance, if the voltage on capacitor C19is 3 volts, then the output voltage from inverter 2332 will be close tozero, while if the voltage on capacitor C19 is close to zero, then theoutput from the inverter 2332 will be at V_(dd) (e.g. 8 volts). Thepresence of the level shifting inverter, therefore, provides severaladvantages. A higher voltage (e.g. 8 volts) is supplied as a switchvoltage to discharge transistors Q18 and Q22. But the 8 volts requiredfor such switching is derived from a power supply, interconnect 2334,which is a DC supply and which only needs to provide enough current tocharge the gate capacitance on various transistors in the pixel. Thepower required to drive the supply interconnect 2334 will, therefore, beonly a minor contributor to the power required to drive shutter assembly2304. At the same time the data voltage, supplied by data interconnect2308 and stored on capacitor C19, can be less than 5 volts (e.g. 3volts) and the power associated with AC voltage variations oninterconnect 2308 will be substantially reduced.

The transition-sharpening inverter 2336 helps to reduce the switchingtime or latency between voltage states as output to the dischargetransistor Q22 and to the switching inverter 2340. Any reduction inswitching time on the inputs to the CMOS switching circuit (Q16 throughQ22) helps to reduce the transient switching currents experienced bythat circuit.

The combination of the CMOS switching circuit, with transistors Q16through Q22, the CMOS switching inverter 2340, and the CMOS levelshifting inverter 2332 makes the control matrix 2300 an attractive lowpower method for driving an array of shutter assemblies 2304. Reliableactuation of even dual-actuator shutter assemblies, such as shutterassembly 2304, is achieved with the use of only a single storagecapacitor, C19, in each pixel.

In control matrix 2300 the global actuation interconnect 2314 isconnected to the source of transistors Q31, Q35, Q39, Q18, and Q22.Maintaining the global actuation interconnect 2314 at a potentialsignificantly above that of the shutter common interconnect 2315prevents the turn-on of any of the transistors Q31, Q35, Q39, Q18, andQ22, regardless of what charge is stored on the capacitor C19. Globalactuation in control matrix 2300 is achieved by bringing the potentialon the global actuation interconnect 2314 to substantially the samepotential as the shutter common interconnect 2315. During the time thatthe global actuation is so activated, all of the transistors Q31, Q35,Q39, Q18, and Q22 have the opportunity to change their state, dependingon what data voltage has been stored on capacitor C19.

The voltage supplied by supply interconnect 2334, V_(dd), is notnecessarily the same as the actuation voltage V_(at), as supplied by thecharge interconnect 2310. Therefore, some optional specifications ontransistors Q16 through Q22 can help to reduce the transient switchingcurrents in control matrix 2300. For instance it may be preferable toincrease the width to length ratio in the discharge transistors Q18 andQ22 as compared to the charge transistors Q16 and Q20. The ratio ofwidth to length for the discharge transistors may vary between 1 and 10while the ratio of length to width for the charge transistors may varybetween 0.1 and 1. Similarly the width to length ratio between levelshifting transistors Q31 and Q33 should be similarly differentiated. Forinstance, the ratio of width to length for transistor Q31 may varybetween 1 and 10 while the ratio of width to length for transistor Q33may vary between 0.1 and 1.

In operation, in order to periodically reverse the polarity of voltagessupplied to the shutter assembly 2304, the control matrix 2300alternates between two control logics as described in relation tocontrol matrix 1600 of FIG. 16A.

Alternative embodiments to control matrix 2300 are also possible. Forinstance, the level shifting inverters 2332 and the transitionsharpening inverter 2336 can be removed from the circuit as long as thevoltage supplied by the data interconnect 2308 is high enough to switchthe flip-flop circuit reliably. As this required switching voltage maybe as high as 8 volts, the power dissipation for such a simplifiedcircuit is expected to increase by comparison to control matrix 2300.The simplified circuit would, however, require less real estate andcould therefore be packed to higher pixel densities.

In another alternative to control matrix 2300, the pre-charge circuitfrom control matrices 2000 and 2100 of FIGS. 20 and 21, respectively,can be substituted into control matrix 2300, in place of transistorsQ16, Q18, Q20, and Q22. For such a control matrix the transitionsharpening inverter 2336 would no longer be necessary. To the extentthat both pMOS and nMOS remain available to this CMOS circuit, bothtypes of transistors would still be beneficial in the level shiftinginverter 2332 and in the switching inverter 2340. This circuit wouldthereby exhibit power dissipation advantages by comparison to controlmatrix 2100 of FIG. 21.

FIG. 24 is yet another suitable control matrix 2440 for inclusion in thedisplay apparatus 100, according to an illustrative embodiment of theinvention. Control matrix 2440 controls an array of pixels 2442 thatinclude dual-actuator shutter assemblies 2444 (i.e., shutter assemblieswith both shutter-open and shutter-close actuators). The actuators inthe shutter assemblies 2444 can be made either electrically bi-stable ormechanically bi-stable.

Control matrix 2440 is substantially the same as control matrix 1640 ofFIG. 16B, except for three changes. A dual-actuator shutter assembly2444 is utilized instead of the elastic shutter assembly 1644, a newcommon drive interconnect 2462 is added, and there is no voltagestabilizing capacitor, such as capacitor 1652, in control matrix 2440.For the example given in control matrix 2440, the common driveinterconnect 2462 is electrically connected to the shutter-open actuatorof the shutter assembly 2444.

Despite the presence of a dual-actuator shutter assembly 2444, thecontrol matrix 2440 includes only a single data interconnect 2448 foreach column of pixels 2442 in the control matrix. The actuators in theshutter assemblies 2444 can be made either electrically bi-stable ormechanically bi-stable.

The control matrix 2440 includes a scan-line interconnect 2446 for eachrow of pixels 2442 in the control matrix 2440. The control matrix 2440further includes a charge interconnect 2450, a global actuationinterconnect 2454, and a shutter common interconnect 2455. Theinterconnects 2450, 2454, 2455, and 2462 are shared among pixels 2442 inmultiple rows and multiple columns in the array. In one implementation(the one described in more detail below), the interconnects 2450, 2454,2455, and 2462 are shared among all pixels 2442 in the control matrix2440.

Each pixel 2442 in the control matrix includes a shutter chargetransistor 2456, a shutter discharge transistor 2458, a shutterwrite-enable transistor 2457, and a data store capacitor 2459 asdescribed in FIGS. 16A and 19. For the example given in control matrix2440 the drain of the shutter discharge transistor is connected to theshutter-close actuator of the shutter assembly 2444.

By comparison to control matrix 1600 of FIG. 16A, the chargingtransistor 2456 is wired with a different circuit connection to thecharge interconnect 2450. Control matrix 2440 does not include a chargetrigger interconnect which is shared among pixels. Instead, the gateterminals of the charging transistor 2456 are connected directly to thecharge interconnect 2450, along with the drain terminal of transistor2456. In operation, the charging transistors operate essentially asdiodes, i.e., they can pass a current in only 1 direction. Theirfunction in the charging circuit becomes equivalent to that of diode1410 in control circuit 1400 of FIG. 14.

A method of addressing and actuating the pixels in control matrix 2440is illustrated by the method 2470 shown in FIG. 25. The method 2470proceeds in three general steps. First the matrix is addressed row byrow by storing data into the data store capacitors 2459. Next allactuators are actuated (or reset) simultaneously (step 2488) in part byapplying a voltage V_(at) to the charge interconnect 2450. And finallythe image is set in steps 2492-2494 by a) selectively activatingtransistors 2458 by means of the global actuation interconnect 2454 andb) changing the potential difference between the common driveinterconnect 2462 and the shutter common interconnect 2455 so as to begreater than an actuation voltage V_(at).

As described with respect to control method 1000 of FIG. 10, or withrespect to control matrix 1400 of FIG. 14, the control matrix 2440 canoperate between two control logics—which provide a periodic polarityreversal and thereby ensure a 0V DC average operation across the shutterassemblies 2442. For reasons of clarity the details for control method2470 are described next with respect to only the first control logic. Inthis first control logic the potential of the shutter commoninterconnect 2455 is maintained at all times near to the groundpotential. A shutter will be held in either the open or closed states byapplying a voltage V_(at) directly across either or both of the chargeinterconnect 2450 or the common drive interconnect 2462. (In the secondcontrol logic, to be described after we complete the discussion of FIG.25, the shutter common interconnect is held at the voltage V_(at), andan actuated state will be maintained by maintaining either or both ofthe charge interconnect 2450 or the common drive interconnect 2462 atground.)

More specifically for the first control logic of method 2470, the frameaddressing cycle of method 2470 begins when a voltage V_(off) is appliedto the global actuation interconnect 2454 (step 2472). The voltageV_(off) on interconnect 2454 is designed to ensure that the dischargetransistor 2458 will not turn on regardless of whether a voltage hasbeen stored on capacitor 2459.

The control matrix 2440 then proceeds with the addressing of each pixel2442 in the control matrix, one row at a time (steps 2474-2484). Toaddress a particular row, the control matrix 2440 write-enables a firstscan line by applying a voltage V_(we) to the corresponding scan-lineinterconnect 2446 (step 2474). Then, at decision block 2476, the controlmatrix 2440 determines for each pixel 2442 in the write-enabled rowwhether the pixel 2442 needs to be open or closed. For example, if atthe reset step 2488 all shutters are to be (temporarily) closed, then atdecision block 2476 it is determined for each pixel 2442 in thewrite-enabled row whether or not the pixel is to be (subsequently)opened. If a pixel 2442 is to be opened, the control matrix 2440 appliesa data voltage V_(d), for example 5V, to the data interconnect 2448corresponding to the column in which that pixel 2442 is located (step2478). The voltage V_(d) applied to the data interconnect 2448 isthereby caused to be stored by means of a charge on the data storecapacitor 2459 of the selected pixel 2442 (step 2479). If at decisionblock 2476, it is determined that a pixel 2442 is to be closed, thecorresponding data interconnect 2448 is grounded (step 2480). Althoughthe temporary (or reset) position after step 2488 in this example isdefined as the shutter-close position, alternative shutter assembliescan be provided in which the reset position after 2488 is a shutter-openposition. In these alternative cases, the application of data voltageV_(d), at step 2478, would result in the opening of the shutter.

The application of V_(we) to the scan-line interconnect 2446 for thewrite-enabled row turns on all of the write-enable transistors 2457 forthe pixels 2442 in the corresponding scan line. The control matrix 2440selectively applies the data voltage to all columns of a given row inthe control matrix 2440 at the same time while that row has beenwrite-enabled. After all data has been stored on capacitors 2459 in theselected row (steps 2479 and 2481), the control matrix 2440 grounds theselected scan-line interconnect (step 2482) and selects a subsequentscan-line interconnect for writing (step 2485). After the informationhas been stored in the capacitors for all the rows in control matrix2440, the decision block 2484 is triggered to begin the global actuationsequence.

The actuation sequence begins at step 2486 of method 2470, with theapplication of an actuation voltage V_(at), e.g. 40 V, to the chargeinterconnect 2450. As a consequence of step 2486, the voltage V_(at) isnow imposed simultaneously across all of the shutter-close actuators ofall the shutter assemblies 2444 in control matrix 2440. Next, at step2487, the potential on the common drive interconnect 2462 is grounded.In this first control logic (with the shutter common potential 2455 heldnear to ground) a grounded common drive interconnect 2462 reduces thevoltage drop across all of the shutter-open actuators of all shutterassemblies 2444 to a value substantially below the maintenance voltageV_(m). The control matrix 2440 then continues to maintain these actuatorvoltages (from steps 2486 and 2487) for a period of time sufficient forall actuators to actuate (step 2488). For the example given in method2470, step 2488 acts to reset and close all actuators into an initialstate. Alternatives to the method 2470 are possible, however, in whichthe reset step 2488 acts to open all shutters. For this case the commondrive interconnect 2462 would be electrically connected to theshutter-closed actuator of all shutter assemblies 2444.

At the next step 2490 the control matrix grounds the charge interconnect2450. The electrodes on the shutter-close actuators in shutter assembly2444 provide a capacitance which stores a charge after the chargeinterconnect 2450 has been grounded and the charging transistor 2456 hasbeen turned off. The stored charge acts to maintain a voltage in excessof the maintenance voltage V_(m) across the shutter-close actuator.

After all actuators have been actuated and held in their closed positionby a voltage in excess of V_(m), the data stored in capacitors 2459 cannow be utilized to set an image in control matrix 2440 by selectivelyopening the specified shutter assemblies (steps 2492-2494). First, thepotential on the global actuation interconnect 2454 is set to ground(step 2492). Step 2492 makes it possible for the discharge switchtransistor 2458 to turn-on in accordance to whether a data voltage hasbeen stored on capacitor 2459. For those pixels in which a voltage hasbeen stored on capacitor 2459, the charge which was stored on theshutter-close actuator of shutter assembly 2444 is now allowed todissipate through the global actuation interconnect 2454.

Next, at step 2493, the voltage on the common drive interconnect 2462 isreturned to the actuation voltage V_(at), or is set such that thepotential difference between the common drive interconnect 2462 and theshutter common interconnect 2455 is greater than an actuation voltageV_(at). The conditions for selective actuation of the pixels have nowbeen set. For those pixels in which a charge (or voltage V_(d)) has beenstored on capacitor 2459, the voltage difference across theshutter-close actuator will now be less than the maintenance voltageV_(m) while the voltage across the shutter-open actuator (which is tiedto the common drive 2462) will at V_(at). These selected shutters willnow be caused to open at step 2494. For those pixels in which no chargehas been stored on capacitor 2459, the transistor 2458 remains off andthe voltage difference across the shutter-close actuator will bemaintained above the maintenance voltage V_(m). Even though a voltageV_(at) has been imposed across the shutter-open actuator, the shutterassembly 2444 will not actuate at step 2494 and will remain closed. Thecontrol matrix 2440 continues to maintain the voltages set after steps2492 and 2493 for a period of time sufficient for all selected actuatorsto actuate during step 2494. After step 2494, each shutter is in itsaddressed state, i.e., the position dictated by the data voltagesapplied during the addressing and actuating method 2470.

To set an image in a subsequent video frame, the process begins again atstep 2472.

In alternate embodiments, the positions of the steps 2486 and 2487 inthe sequence can be switched, so that step 2487 occurs before step 2486.

In the method 2470, all of the shutters are closed simultaneously duringthe time between step 2488 and step 2494, a time in which no imageinformation can be presented to the viewer. The method 2470, however, isdesigned to minimize this dead time (or reset time), by making use ofdata store capacitors 2459 and global actuation interconnect 2454 toprovide timing control over the transistors 2458. By the action of step2472, all of the data for a given image frame can be written to thecapacitors 2459 during the addressing sequence (steps 2474-2485),without any immediate actuation effect on the shutter assemblies. Theshutter assemblies 2444 remain locked in the positions they wereassigned in the previous image frame until addressing is complete andthey are uniformly actuated or reset at step 2488. The global actuationstep 2492 allows the simultaneous transfer of data out of the data storecapacitors 2459 so that all shutter assemblies can be brought into theirnext image state at the same time.

As with the previously described control matrices, the activity of anattached backlight can be synchronized with the addressing of eachframe. To take advantage of the minimal dead time offered in theaddressing sequence of method 2470, a command to turn the illuminationoff can be given between step 2484 and step 2486. The illumination canthen be turned-on again after step 2494. In a field-sequential colorscheme, a lamp with one color can be turned off after step 2484 while alamp with either the same or a different color is turned on after step2494.

In other implementations, it is possible to apply the method 2470 ofFIG. 25 to a selected portion of the whole array of pixels, since it maybe advantageous to update different areas or groupings of rows andcolumns in series. In this case a number of different chargeinterconnects 2450, global actuation interconnects 2454, and commondrive interconnects 2462 could be routed to selected portions of thearray for selectively updating and actuating different portions of thearray.

As described above, to address the pixels 2442 in the control matrix2440, the data voltage V_(d) can be significantly less than theactuation voltage V_(at) (e.g., 5V vs. 40V). Since the actuation voltageV_(at) is applied once a frame, whereas the data voltage V_(d) may beapplied to each data interconnect 2448 as may times per frame as thereare rows in the control matrix 2440, control matrices such as controlmatrix 2440 may save a substantial amount of power in comparison tocontrol matrices which require a data voltage to be high enough to alsoserve as the actuation voltage.

It will be understood that the embodiment of FIG. 24 assumes the use ofn-channel MOS transistors. Other embodiments are possible that employp-channel transistors, in which case the relative signs of the biaspotentials V_(at) and V_(d) would be reversed.

In operation, the control matrix alternates between two control logicsas described with respect to control method 1000 of FIG. 10, or withrespect to control matrix 1400 of FIG. 14. The two control logicsprovide a periodic polarity reversal and thereby ensure a 0V DC averageoperation across the shutter assemblies 2442. To achieve polarityreversal in the second control logic several of the voltage assignmentsillustrated and described with respect to method 2470 of FIG. 25 arechanged, although the sequencing of the control steps remains the same.

In the second control logic, the potential on the shutter commoninterconnect 2455 is maintained at a voltage near to V_(at) (instead ofnear ground as was the case in the first control logic). In the secondcontrol logic, at step 2478, where the logic is set for the opening of ashutter assembly, the data interconnect 2448 is grounded instead oftaken to V_(d). At step 2480, where the logic is set for the closing ofa shutter assembly, the data interconnect is taken to the voltage V_(d).Step 2486 remains the same, but at step 2487 the common driveinterconnect is set to the actuation voltage V_(at) in the secondcontrol logic instead of to ground. At the end of step 2487 in thesecond control logic, therefore, each of the shutter common interconnect2455, the common drive interconnect 2462, and the charge interconnect2450 are set to the same voltage V_(at). The image setting sequence thencontinues with grounding of the global actuation interconnect 2454 atstep 2492—which has the effect in this second logic of closing onlythose shutters for which a voltage V_(d) was stored across the capacitor2459. At step 2493 in the second control logic the common driveinterconnect 2462 is grounded. This has the effect of actuating andopening any shutters that were not otherwise actuated at step 2492. Thelogical state expressed at step 2494, therefore, is reversed in thesecond control logic, and the polarities are also effectively reversed.

Generally speaking any of the control matrices 1100, 1300, 1400, 1500,or 1700, which were illustrated through the use of single-actuated orelastic shutter assemblies, can be adapted advantageously for use with adual-actuated shutter assembly such as 1904 by reproducing the controlcircuit in mirror fashion for each of the open and closed actuators. Asshown in method 800 of FIG. 8, the data supplied to the data-openinterconnects and the data-closed interconnects will often becomplementary, i.e. If a logical “1” is supplied to the data-openinterconnect then a logical “0” will typically be supplied to the dataclosed interconnect. In additional alternative implementations, thecontrol matrices can be modified to replace the transistors withvaristors.

In alternative implementations, the control matrix keeps track of theprior position of each pixel and only applies positions to the datainterconnects corresponding to a pixel if the state of the pixel for thenext image frame is different than the prior position. In anotheralternative embodiment, the pixels include mechanically bi-stableshutter assemblies instead of just electrically bi-stable shutterassemblies. In such an embodiment, the charge trigger transistors can bereplaced with resistors and the charge trigger interconnect can beomitted from the control matrix, as described above in relation to FIG.18. The dual control logic used by control matrix 1400 may also beutilized in other implementations of control matrix 1800.

FIG. 26 is a schematic diagram of yet another suitable control matrix2640 for inclusion in the display apparatus 100, according to anillustrative embodiment of the invention. Control matrix 2640 controlsan array of pixels 2642 that include dual-actuator shutter assemblies2644 (i.e., shutter assemblies with both shutter-open and shutter-closeactuators). The actuators in the shutter assemblies 2004 can be madeeither electrically bi-stable or mechanically bi-stable.

Control matrix 2640 is substantially the same as control matrix 2440,with two changes: a charge trigger interconnect 2652 has been added anda pMOS transistor has been substituted for the charging transistor 2656instead of the nMOS transistor as was indicated at 2456.

The control matrix 2640 utilizes a dual-actuator shutter assembly 2644along with a common drive interconnect 2662. For the example given incontrol matrix 2640 the common drive interconnect 2662 is electricallyconnected to the shutter-open actuator of the shutter assembly 2644.Despite the presence of a dual-actuator shutter assembly 2644, thecontrol matrix 2640 includes only a single data interconnect 2648 foreach column of pixels 2642 in the control matrix.

The control matrix 2640 includes a scan-line interconnect 2646 for eachrow of pixels 2642 in the control matrix 2640. The control matrix 2640further includes a charge interconnect 2650, a charge triggerinterconnect 2652, a global actuation interconnect 2654, and a shuttercommon interconnect 2655. The interconnects 2650, 2654, 2655, and 2662are shared among pixels 2642 in multiple rows and multiple columns inthe array. In one implementation (the one described in more detailbelow), the interconnects 2650, 2654, 2655, and 2662 are shared amongall pixels 2642 in the control matrix 2640.

Each pixel 2642 in the control matrix includes a shutter chargetransistor 2656, a shutter discharge transistor 2658, a shutterwrite-enable transistor 2657, and a data store capacitor 2659 asdescribed in FIGS. 16 and 18. For the example given in control matrix2644 the drain of the shutter discharge transistor is connected to theshutter-close actuator of the shutter assembly 2644.

The control matrix 2640 makes use of two complementary types oftransistors: both p-channel and n-channel transistors. It is thereforereferred to as a complementary MOS control matrix or a CMOS controlmatrix. While the charging transistor 2656 is made of the pMOS type, thedischarge transistor 2658 is made of the nMOS type of transistor. (Inother implementations the types of transistors can be reversed, forexample nMOS transistors can be used for the charging transistors andpMOS transistors can be used for the discharge transistors.) The use ofa charge trigger interconnect along with the CMOS circuit helps toreduce the set of voltage variations required to achieve shutteractuation.

With the use of the charge trigger interconnect 2652, the controlcircuit 2640 is wired to the charging transistor 2656 in a fashionsimilar to that of control matrix 1600. Only the source of pMOStransistor 2656 is connected to the charge interconnect 2650 while thegate is connected to the charge trigger interconnect 2652. Throughoutoperation, the charge interconnect 2650 is maintained at a constantvoltage equal to the actuation voltage V_(at). The charge triggerinterconnect 2652 is maintained at the same voltage (V_(at)) as that ofthe charge interconnect whenever the charge transistor 2656 is to beheld in the off state. In order to turn-on the charge transistor 2656,the voltage on the charge trigger interconnect 2652 is reduced so thatthe voltage difference between charge interconnect 2650 and interconnect2652 is greater than the threshold voltage of the transistor 2656.Threshold voltages can vary in a range from 2 to 8 volts. In oneimplementation where the transistor 2656 is a pMOS transistor, both thecharge interconnect 2650 and the charge trigger interconnect 2652 areheld at a V_(at) of 40 volts when the transistor 2656 is off. In orderto turn transistor 2656 on, the voltage on the charge interconnect 2650would remain at 40 volts while the voltage on the charge triggerinterconnect 2652 is temporarily reduced to 35 volts. (If an nMOStransistor were to be used at the point of transistor 2656, then theV_(at) would be −40 volts and a charge trigger voltage of −35 voltswould be sufficient to turn the transistor on.)

A method for addressing and actuating pixels in control matrix 2640 issimilar to that of method 2470, with the following changes. At step 2486the voltage on the charge trigger interconnect is reduced from V_(at) toV_(at) minus a threshold voltage. Similar to the operation of method2470 all of the shutter-closed actuators then become charged at the sametime, and at step 2488 all shutters will close while a constant voltageV_(at) is maintained across the shutter close actuator. In anothermodification to the method 2470, at step 2490, the charge interconnect2650 is allowed to remain at V_(at) while the transistor 2656 is turnedoff by returning the voltage on the charge trigger interconnect 2652 toV_(at). After the transistor 2656 is turned off, the actuation procedureproceeds to the global actuation step 2492.

The actuator charging process at step 2486 in method 2470 can beaccomplished as described above for control matrix 2640 with nearly zerovoltage change on the charge interconnect 2650 and only a minimal(threshold voltage) change required for the charge trigger interconnect2652. Therefore the energy required to repeatedly change the voltagefrom Vat to ground and back is saved in this control matrix. The powerrequired to drive each actuation cycle is considerably reduced incontrol matrix 2640 as compared to control matrix 2440.

In a similar fashion, the use of complementary nMOS and pMOS transistortypes can be applied to the charging transistors in control matrices1500, 1600, 1700, 1800, 1900, 2000, 2100, 2200, and 2300 to reduce thepower required for actuation.

FIG. 27 is a schematic diagram of another control matrix 2740 suitablefor inclusion in the display apparatus 100, according to an illustrativeembodiment of the invention. Control matrix 2740 operates in a mannersubstantially similar to that of control matrix 2440, except that someof the circuit elements are now shared between multiple shutterassemblies in the array of shutter assemblies. In addition several ofthe common interconnects are wired into separate groups, such that eachof these common interconnects are shared only amongst the pixels oftheir particular group.

The control matrix 2740 includes an array of dual-actuator shutterassemblies 2744. Similar to the control matrix 2440, however, thecontrol matrix 2740 includes only a single data interconnect 2748 foreach column of pixels 2742 in the control matrix. The actuators in theshutter assemblies 2744 can be made either electrically bi-stable ormechanically bi-stable.

The control matrix 2740 includes one scan-line interconnect 2746 whichis shared amongst four consecutive rows of pixels 2742 in the array ofpixels. Each pixel in the array is also connected to a global actuationinterconnect, a common drive interconnect, a charge interconnect, and ashutter common interconnect. For the embodiment illustrated in FIG. 27,however, the pixels are identified as members of four separate groupswhich are connected in common only to certain interconnects within theirparticular group. The pixels 2742A, for instance, are aligned along thefirst row and are members of the first group in control matrix 2740.Each pixel in the group of pixels that include pixels 2742A is connectedto a global actuation interconnect 2754A and a common drive interconnect2762A. The pixels 2742B are aligned along the second row and are membersof the second group in control matrix 2740. Each pixel in the group ofpixels 2742B is connected to a global actuation interconnect 2754B and acommon drive interconnect 2762B. Similarly the pixels 2742C in the thirdrow are members of the third group of pixels which are connected incommon to global actuation interconnect 2754C and common driveinterconnect 2762C. Similarly the pixels 2742D in the third row aremembers of the third group of pixels which are connected in common toglobal actuation interconnect 2754D and common drive interconnect 2762D.The sequential pattern of rows including pixels 2742A, 2742B, 2742C, and2742D is repeated for rows that continue both above and below the pixelsillustrated in FIG. 27. Each group of four rows includes a single scanline interconnect 2746 which is shared between the four rows.

The global actuation interconnects 2754A, 2754B, 2754C, and 2754D areelectrically independent of each other. A global actuation signalapplied to the interconnect 2754A may actuate all pixels 2742A withinthat row of the array, as well as all pixels in similarly connected rows(that occur in every fourth row of the array). A global actuation signalapplied to the interconnect 2754A, however, will not actuate any of thepixels in the other groups, e.g. it will not actuate the pixels 2742B,2742C, or 2742D. In a similar fashion the common drive interconnects2762A, 2762B, 2762C, and 2762D are electrically independent, connectingto all pixels within their particular group but not to any pixelsoutside of their group.

The control matrix 2740 further includes a charge interconnect 2750 anda shutter common interconnect 2755. The interconnects 2750 and 2755 areshared among pixels 2742 in multiple rows and multiple columns in thearray. In one implementation (the one described FIG. 27), theinterconnects 2750 and 2755 are shared among all pixels 2742 in thecontrol matrix 2740.

Each pixel 2742 in the control matrix includes a shutter chargetransistor 2756 and a shutter discharge transistor 2758. As described inFIG. 16B and FIG. 24 the charge transistor 2756 is connected between thecharge interconnect 2750 and the shutter-closed actuator of shutterassemblies 2744 in each pixel. The shutter discharge transistor 2758 isconnected between the shutter assembly 2744 and the particular globalactuation interconnect 2754A, 2754B, 2754C, or 2754D assigned to itsgroup. For the example given in control matrix 2740 the common driveinterconnects 2762A, 2762B, 2762C, and 2762D are electrically connectedto the shutter-open actuators of the shutter assemblies 2744 withintheir particular groups.

Near to the intersection of each data interconnect 2748 and each scanline interconnect 2746 is a write-enable transistor 2757, and a datastore capacitor 2759. The transistors 2757 and capacitor 2759 appear ineach column but, like the scan line interconnect 2746, they appear onlyonce in every four rows. The function of these circuit elements isshared between the pixels in each of the four adjacent rows. A fan-outinterconnect 2766 is used to connect the charge stored on the capacitor2759 to the gates on each of the shutter discharge transistors 2758within the column for the four adjacent rows.

The operation of shutter assemblies 2744 is very similar to thatdescribed for control matrix 2440 in method 2470. The difference isthat, for control matrix 2740, the addressing and actuating of thepixels is carried out independently and during separate time intervalsfor each of the four pixel groups 2742A, 2742B, 2742C, and 2742D. Forthe embodiment of FIG. 27 the addressing for the pixels in group 2742Awould proceed by applying Voff to the global actuation interconnect2754A and applying a write-enable voltage to each of the scan lineinterconnects 2746 in turn. During the time that a scan line iswrite-enabled the data corresponding to each of the pixels of group Aassigned to a particular scan line is loaded into the capacitor 2759 bymeans of the data interconnect 2748 in each column. After the addressingof the scan lines in the whole array is complete, the control matrixthen proceeds to an actuation sequence as described from step 2486 tostep 2494 in the method 2470. Except, for control matrix 2740, the datais loaded for only one group of pixels at a time (e.g. the pixels 2742Ain group A) and the actuation proceeds by activating only the globalactuation interconnect (2754A) and the common drive interconnect (2762A)for that particular group of pixels.

After actuation of pixels 2742A is complete, the control matrix proceedswith the loading of data into the second group of pixels, e.g. 2742B.The addressing of the second group of pixels (group B) proceeds by useof the same set of scan line interconnects 2746, data interconnects2748, and data store capacitors 2759 as were employed for group A. Thedata stored in capacitors 2759 will only affect the actuation of thepixels 2742B in group B, however, since this data can only betransferred to the shutter assemblies of their particular group afteractuation by means of the global actuation interconnect for the group,2754B. The selective actuation of each the four pixel groups isaccomplished by means of the independent global actuation interconnects2754A, 2754B, 2754C, or 2754D and independent common drive interconnects2762A, 2762B, 2762C, or 2762D.

In order to address and actuate all pixels in the array it is necessaryto address and actuate the pixels in each of the four pixel groups2742A, 2742B, 2742C, and 2742D sequentially. Considerable space savings,however, is accomplished in the array since the write enable transistors2757 and the data store capacitors 2759 only need to be fabricated oncefor each adjacent set of four rows.

For the embodiment given in FIG. 27 the pixels in the array have beenbroken into four groups A, B, C, and D. Other embodiments are possible,however, in which the array can be broken into only 2 groups, into 3groups, into 6 groups, or into 8 groups. In all of these cases thepixels of a group are connected in common to their own particular globalactuation interconnect and common drive interconnect. For the case of 2groups the scan line interconnect, the write-enable transistor, and thedata store capacitor would appear in every other row. For the case of 6groups the scan line interconnect, the write-enable transistor, and thedata store capacitor would appear in every sixth row.

For the embodiment given in FIG. 27 the charge interconnect 2750 andshutter common interconnect 2755 are shared among pixels 2742 inmultiple rows and multiple columns in the array. In other embodimentsthe charge interconnects and shutter common interconnects can also beassigned and shared only among particular groups, such as groups A, B,C, and D.

The sharing of actuation interconnects amongst distinct groups, and thesharing of scan line interconnects, write-enable transistors, and datastore capacitors amongst adjacent rows has been described in animplementation particular to the control matrix 2440. Similar sharing ofpixel elements, however, can be adopted with respect to a number ofother control matrices, such as control matrices 1400, 1500, 1600, 1640,1700, 1800, 1900, 2000, 2100, 2200, 2300, and 2640.

Voltage vs. Charge Actuation

As described above, in various embodiments of the invention, theMEMS-based light modulators used to form an image utilize electrostaticactuation, in which opposing capacitive members are drawn togetherduring an actuation event. In some actuator implementations, dependingon the geometry of the electrostatic members, the force drawing thecapacitive members will vary in relation to the voltage applied acrossthe electrostatic members. If the charge stored on the actuator is heldconstant, then the voltage and thus the force attracting the capacitivemembers, may decrease as the capacitive beams draw closer together. Forsuch actuators, it is desirable to maintain a substantially constantvoltage across the capacitive members to maintain sufficient force tocomplete actuation. For other actuator geometries (e.g., parallel platecapacitors), force is proportional to the strength of the electric fieldbetween the capacitive portions of the actuator, the electric fieldlikewise being proportional to the amount of charge stored on thecapacitive members. In such actuators, if an elastic restoring force ispresent which increases as capacitive members draw together, it may benecessary to increase the stored charge on the members to complete theactuation. An increase in stored charge and therefore the force ofactuation can be accomplished by connecting the actuator to a source ofcharge, i.e. a constant voltage source.

Control matrix 1900 of FIG. 19 operates in conditions in which actuatorsare electrically isolated from a source of charge during actuation.Prior to actuation of either of the two actuators included in the pixel,charge yielding a voltage sufficient to initiate actuation of bothactuators V_(at), absent a maintenance voltage, is stored directly oneach actuator. The actuators are then isolated from external voltagesources. At a later date, the charge stored on one of the actuators isdischarged. The non-discharged actuator then actuates based solely onthe constant charge previously stored on the actuator.

FIG. 28 includes three charts that illustrate the variations inelectrostatic parameters that result from movement of portions ofelectrostatic actuators in various implementations of the invention. Thechart labeled Case A in FIG. 28 illustrates the variations in parametersassociated with the actuation of the actuator of a pixel from controlmatrix 1900 from an open position to a closed position. Duringactuation, since the actuator is electrically isolated, the chargeremains constant. As the capacitive members draw closer together, thevoltage decreases and the capacitance increases. To ensure properactuation, the initial voltage applied to the actuator is preferablyhigh enough such that as the voltage decreases resulting from motion ofportions of the actuator, the resulting voltage is still sufficient tofully actuate the actuator.

To help ensure proper actuation without applying what might otherwise bean unnecessarily high voltage across the capacitive members of anactuator, a control matrix can incorporate a voltage regulator inelectrical communication with the actuator during actuation of theactuator. The voltage regulator maintains a substantially constantvoltage on the actuator during actuation. As a result, as thecapacitance of the actuator increases as the capacitive elements drawcloser together, additional charge flows into the capacitive members tomaintain the voltage across the capacitive members, thereby maintainingthe voltage level, increasing the electric field, and increasing theattractive force between the capacitive members. Thus, the voltageregulator substantially limits variations in voltage that wouldotherwise be caused by movement of portions of the actuators duringactuation.

Voltage regulators can be included in each pixel in a control matrix,for example, as stabilizing capacitors connected to the capacitivemembers of the actuators. Control matrices 500, 700, 900, 1400, 1500,1640, 1800, 2000, and 2100 include such stabilizing capacitors. Theimpact of such a stabilizing capacitor is depicted in the chart labeledas Case B in FIG. 28. In such implementations, as the capacitive membersof an actuator draw closer together, charge stored on the stabilizingcapacitor flows into the capacitive member maintaining a voltageequilibrium between the stabilizing capacitor and the actuator. Thus,the voltage on the actuator decreases, but less so than in controlmatrices without a stabilizing capacitor. Preferably, the stabilizingcapacitor is selected such that during actuation, the variation in thevoltage on the actuator is limited to less than about 20% of V_(at). Inother implementations, a higher capacitance capacitor is selected suchthat during actuation, the variation in the voltage on the actuator islimited to less than about 10% of V_(at). In still otherimplementations, the stabilizing capacitor is selected such that duringactuation, the variation in the voltage on the actuator is limited toless than about 5% of V_(at).

Alternatively, display drivers may serve as voltage regulators. Thedisplay drivers output a DC actuation voltage. In some implementations,the voltage may be substantially constant throughout operation of thedisplay apparatus in which it is incorporated. In such implementations,the application of the voltage output by the display drivers isregulated by transistors incorporated into each pixel in the controlmatrix. In other implementations, the display drivers switch between twosubstantially constant voltage levels according. In suchimplementations, no such transistors are needed. In some implementationsthe pixels are connected to the display drivers by means of a voltageactuation interconnect. In some implementations, such as control matrix2640, a voltage actuation interconnect such as interconnect 2662, can bea global common interconnect, meaning that it connects to pixels in atleast two rows and two columns of the array of pixels.

Control matrices 600, 1100, 1300, 1600, 1700, 1900, 2200, 2300, 2440,2640, and 2740 include voltage regulators in the form of connections tovoltage sources. As illustrated in Case C of FIG. 28, as the capacitivemembers of an electrostatic actuator connected to a voltage source drawtogether, the voltage across the capacitive members remainssubstantially constant. To maintain the constant voltage despiteincreasing capacitance, additional charge flows into the capacitivemembers as the capacitance of the actuator increases.

Gray Scale Techniques Field Sequential Color

The display apparatus 100 provides high-quality video images usingrelatively low power. The optical throughput efficiency of ashutter-based light valve can be an order of magnitude higher thanafforded by liquid crystal displays, because there is no need forpolarizers or color filters in the production of the image. As describedin U.S. patent application Ser. No. 11/218,690, filed on Sep. 2, 2005, aregenerative light guide can be designed which allows for 75% of thelight produced in a backlight to be made available to a viewer.

Without the use of color filters, one method for producing video imagesin a shutter-based display is the use of field-sequential color. Colorfilters reduce the optical efficiency by >60% through absorption in thefilters. Displays utilizing field sequential color instead use abacklight which produces pure red, green and blue light in an orderedsequence. A separate image is generated for each color. When theseparate color images are alternated at frequencies in excess of 50 Hz,the human eye averages the images to produce the perception of a singleimage with a broad and continuous range of colors. Efficient backlightscan now be produced that allow fast switching between pure colors fromeither light-emitting diode (LED) sources or electroluminescent sources.

The control matrices illustrated in FIGS. 5, 6, 7, 9, 11, 13-19 providemeans for generating color-specific images (color sub-frame images),with accurate gray-tones, and the means for switching between colorimages in rapid fashion.

Formation of accurate images with field-sequential color can be improvedby synchronization between the backlight and the pixel addressingprocess, especially since it requires a finite period of time to switchor reset each pixel between the required states of each color sub-frame.Depending on the control matrix used to address and actuate the pixels,if the option of global actuation is not employed, then the imagecontroller may need to pause at each row or scan line of the displaylong enough for the mechanical switching or actuation to complete ineach row. If the backlight were to broadly illuminate the whole displayin a single color while the display controller was switching states, rowby row, between 2 color images, then the resulting contrast would beconfused.

Consider two examples illustrating the blanking times that can beemployed with the backlight during resetting of an image between colorsin a synchronized display. If the shutters require 20 microseconds toactuate or move between open and closed states, if the shutters areactuated in a row-by-row fashion, and if there are 100 rows, then itwould require 2 milliseconds to complete the addressing. Thesynchronized backlight might then be turned-off during those 2milliseconds. Note that if the display runs at a 60 Hz frame rate with 3colors per frame, then there is only 5.6 msec allowed per colorsub-frame and, in this example, the backlight would be off 36% of thetime.

Alternately, when using a global actuation scheme for switching betweencolor sub-frames, the same resetting of the image would require only 20microseconds for the simultaneous movement of all shutters betweenimages. The requirements for shutter speed are now substantiallyrelaxed. If, during the color reset, the backlight were to be off for asmuch as 100 microseconds, the percentage of illumination time at 60 Hzframe rate is now better than 98%. Assuming a 100 microsecond imagerefresh time, it is now possible to increase the frame rate to 120 Hzwith no substantial loss in illumination time. Using a frame rate of 120Hz substantially reduces image artifacts induced by field sequentialcolor, such as color breakup in fast moving video images.

Gray Scale

The number of unique colors available in the display is dependant inpart on the levels of gray scale that are available within each of thethree color images. Four principle methods of producing gray scale andcombinations thereof are applicable to the transverse shutter displays.

Analog Gray Scale

The first method of producing gray scale is an analog method, by whichthe shutters are caused to only partially obstruct an aperture inproportion to the application of a partial actuation voltage. Transverseshutters can be designed such that the percent of transmitted light isproportional to an actuation voltage, for instance through control ofthe shape of the actuation electrodes as described above in relation toFIG. 2 and in more detail in U.S. patent application Ser. No. 11/251,035referenced above.

For analog gray scale, the display apparatus is equipped with a digitalto analog converter such that the voltage delivered to the pixels isproportional to the intended gray scale level. The proportional voltageon each actuator is maintained throughout the period of an image framesuch that the proportional shutter position is maintained throughout theillumination period. The optional use of a capacitor placed in parallelwith the actuators in FIGS. 2 and 17 helps to ensure that, even thoughsome charge may leak from the pixel during the time of illumination, thevoltage does not change appreciably so as to alter the shutter positionduring the period of illumination.

The analog gray scale has the advantage of requiring only 1 shutter inmotion per pixel and the setting of only 1 image frame during the periodof each color illumination. The data rates and addressing speeds foranalog gray scale are therefore the least demanding amongst allalternative methods of gray scale.

Time Division Gray Scale

With proper design of the transverse shutter, a low voltage switchingcan be achieved which is fast. Transversely driven shutter assemblies,as described in U.S. patent application Ser. No. 11/251,035 referencedabove, can be built having actuation times in the range of 3microseconds to 100 microseconds. Such rapid actuation makes possiblethe implementation of time division gray scale, wherein the contrast isachieved by controlling the relative on-times or duty cycles of theactuated shutters. A time division gray scale can be implemented usingdigital gray scale coding, in that control matrices incorporatingbi-stable shutter assemblies recognize two states of shutter actuation,on or off. Gray scale is achieved by controlling the length of time ashutter is open.

The switching times can be appreciated by assuming the case of a 60 Hzframe rate with field sequential color. Each color sub-frame is allotted5.6 msec. If the available time interval were to be divided into 63segments (6-bit gray scale per color), then the smallest increment ofon-time for each image, known as the least significant bit time (LSB),would be 88 microseconds. If an image for the LSB time-bit were to beconstructed and displayed using a global actuation scheme, then theactuation of all shutters would need to be completed in significantlyless than the 88 microsecond LSB time. If the display is addressed in arow-by-row basis then the time available for reset at each row isconsiderably less. For a display with 100 rows, the available actuationtime can be less than 0.5 microseconds per row. A number of controlleralgorithms are possible for relaxing the time intervals required foraddressing shutters in a row-by-row scheme (see for example N. A. Clarket al., Ferroelectrics, v. 46, p. 97 (2000)), but in any case the timerequired for shutter actuation in the 6-bit gray scale example isconsiderably less than 20 microseconds.

Achieving multiple bits of gray scale through the use of time divisionmultiplexing requires significant power in the addressing circuitry,since the energy lost in the actuation cycle is ½ CV² for each pixelthrough each refresh or addressing cycle in the control scheme (C is thecapacitance of the pixel plus control electrodes and V is the actuationvoltage). The circuit diagrams of FIGS. 11 and 13-19 reduce powerrequirements by decoupling and reducing the addressing voltages (thevoltages required on the scan lines and data lines) from the actuationvoltages (the voltages required to move a shutter).

Area Division Gray Scale

Another method that can reduce the addressing speed and powerrequirements of the time division gray scale is to allow for multipleshutters and actuators per pixel. A 6 bit binary time-division scheme(63 required time slots) can be reduced to a 5 bit time scheme (31required time slots) by adding the availability of an additional grayscale bit in the spatial or area domain. The additional spatial bit canbe accomplished with 2 shutters and apertures per pixel, especially ifthe shutters/apertures have unequal area. Similarly, if 4 shutters (withunequal areas) are available per pixel then the number of required timebits can be reduced to 3 with the result still being an effective 64levels of gray scale per color.

Illumination Gray Scale

Another method that can relax the speed and/or real estate requirementsfor the above gray scale techniques is use of an illumination grayscale. The contrast achieved through the illumination of the color imagecan be adjusted or given finer gray levels by means of altered intensityfrom the backlight. If the backlight is capable of fast response (as inthe case of LED backlights), then contrast can be achieved by eitheraltering the brightness of the backlight or the duration of itsillumination.

Let us consider one example, wherein it is assumed that the controlmatrix utilizes a global actuation scheme and that time division grayscale is accomplished through construction and display of distincttime-bit images illuminated for differing lengths of time. Take forexample a 4-bit binary time coding scheme accomplished by dividing thecolor frame into 15 time slots. The image that is constructed for theshortest (LSB) time should be held for 1/15 of the available frame time.In order to expand to a 5-bit coding scheme one could, in the timedomain, divide the color frame into 31 time slots, requiring twice theaddressing speed. Alternately, one could assign only 16 time slots andassign to one of these time slots an image that is illuminated at only ½the brightness or by a backlight that is flashed for an on period ofonly 1/31 of the frame time. As many as 3 additional bits of gray scalecan be added on top of a 4 bit time-division coding scheme by addingthese short time-duration images accompanied by partial illumination. Ifthe partial illumination bits are assigned to the smallest of the timeslices, then a negligible loss of average projected brightness willresult.

Hybrid Gray Scale Schemes

The four principle means of gray scale are analog gray scale, timedivision gray scale, area division gray scale, and illumination grayscale. It should be understood that useful control schemes can beconstructed by combinations of any of the above methods, for instance bycombining the use of time division, area division and the use of partialillumination. Further divisions of gray scale are also available throughinterpolation techniques, also known as dither. Time domain ditherincludes the insertion of LSB time bits only in an alternating series ofcolor frames. Spatial domain dither, also known as half-toning, involvesthe control or opening of a specified fraction of neighboring pixels toproduce localized areas with only partial brightness.

The invention may be embodied in other specific forms without departingfrom the spirit or essential characteristics thereof. The forgoingembodiments are therefore to be considered in all respects illustrative,rather than limiting of the invention.

1. A display apparatus comprising: a substrate; an array of pixels,wherein each pixel includes: at least one actuator; and at least oneMEMS device capable of modulating light, wherein each of the MEMSdevices can be driven to at least three states, including: asubstantially open state, a substantially closed state, and a partiallyopen state; and a control matrix for driving each of the MEMS devices inthe array of pixels into one of the at least three states.
 2. Thedisplay apparatus of claim 1, wherein the control matrix drives a MEMSdevice into the substantially open state by applying an actuationvoltage across the at least one actuator.
 3. The display apparatus ofclaim 2, wherein the control matrix drives a MEMS device into thesubstantially closed state by applying an actuation voltage across theat least one actuator.
 4. The display apparatus of claim 3, wherein thecontrol matrix drives a MEMS device into the partially open state byapplying an intermediate voltage across the at least one actuator. 5.The display apparatus of claim 4, wherein the intermediate voltage isbetween a ground voltage and the actuation voltage.
 6. The displayapparatus of claim 3, wherein the at least one actuator comprisesopposing first and second actuators.
 7. The display apparatus of claim6, wherein the control matrix drives a MEMS device into the partiallyopen state by applying a pair of complementary voltages that, whenapplied simultaneously across the opposing first and second actuators,results in controlled states of partial opening.
 8. The displayapparatus of claim 1, wherein the control matrix includes: a pluralityof scan-line interconnects running in a first direction, each enabling aplurality of pixels along the first direction to respond to datavoltages; and a plurality of data interconnects running in a seconddirection perpendicular to the first direction, each providing datavoltages to a plurality of pixels along the second direction.
 9. Thedisplay apparatus of claim 1, wherein the substrate is transparent. 10.The display apparatus of claim 1, wherein the MEMS device modulateslight by moving transversely through a path of a propagating ray oflight.
 11. The display apparatus of claim 1, further comprising arestoring spring opposing the at least one actuator.
 12. The displayapparatus of claim 1, wherein the control matrix includes: an actuationvoltage interconnect for applying an actuation voltage to the at leastone actuator; a grayscale switch electrically connected between theactuation voltage interconnect and the at least one actuator; and a datavoltage interconnect coupled to the grayscale switch, wherein a datavoltage on the data voltage interconnect controls the grayscale switch.13. The display apparatus of claim 12, wherein the actuation voltageapplied to the at least one actuator varies in proportion to the datavoltage resulting in an incremental displacement of the MEMS device. 14.The display apparatus of claim 13, wherein the controller drives a MEMSdevice into one of the at least three states based at least in part onthe magnitude of the data voltage applied to the data voltageinterconnect.
 15. The display apparatus of claim 14, wherein thecontroller drives a MEMS device into one of the at least three statesbased at least in part on the duration of the data voltage applied tothe data voltage interconnect.
 16. The display apparatus of claim 12,further comprising a data store capacitor electrically coupled to thedata voltage interconnect for storing the data voltage corresponding tothe one of at least three states of the MEMS device.
 17. A method fordisplaying an image frame, comprising: applying a write-enabling voltageto a scan-line interconnect in a first row of an array of MEMS devices;applying a data voltage to at least one data-interconnect for a firstMEMS device in the first row of the array; and actuating the first MEMSdevice to drive the first MEMS device into the one of at least threestates: a substantially open state, a substantially closed state, and apartially open state.
 18. The method of claim 17, wherein the partiallyopen state includes a range of partially open states between thesubstantially open state and the substantially closed state.
 19. Themethod of claim 18, wherein the range of partially open states includesdiscrete ranges of partial MEMS device opening.
 20. The method of claim17, wherein displacement of the MEMS device is proportional to the datavoltage.
 21. The method of claim 17, wherein the data voltage comprisesan analog data voltage.